中科院研究生院課程VLSI測試與可測試性設(shè)計.ppt

上傳人:za****8 文檔編號:15855488 上傳時間:2020-09-09 格式:PPT 頁數(shù):51 大小:585.14KB
收藏 版權(quán)申訴 舉報 下載
中科院研究生院課程VLSI測試與可測試性設(shè)計.ppt_第1頁
第1頁 / 共51頁
中科院研究生院課程VLSI測試與可測試性設(shè)計.ppt_第2頁
第2頁 / 共51頁
中科院研究生院課程VLSI測試與可測試性設(shè)計.ppt_第3頁
第3頁 / 共51頁

下載文檔到電腦,查找使用更方便

14.9 積分

下載資源

還剩頁未讀,繼續(xù)閱讀

資源描述:

《中科院研究生院課程VLSI測試與可測試性設(shè)計.ppt》由會員分享,可在線閱讀,更多相關(guān)《中科院研究生院課程VLSI測試與可測試性設(shè)計.ppt(51頁珍藏版)》請在裝配圖網(wǎng)上搜索。

1、1,中科院研究生院課程:VLSI測試與可測試性設(shè)計,第5講 測試生成(1) 李曉維 中科院計算技術(shù)研究所 Email: ,2,Chapter 4,Test Generation,3,What is this chapter about?,Introduce the basic concepts of ATPG Focus on a number of combinational and sequential ATPG techniques Deterministic ATPG and simulation-based ATPG Fast untestable fault identificat

2、ion ATPG for various fault models,4,Test Generation,Introduction Random Test Generation Theoretical Foundations Deterministic Combinational ATPG Deterministic Sequential ATPG Untestable Fault Identification Simulation-based ATPG ATPG for Delay and Bridge Faults Other Topics in Test Generation Conclu

3、ding Remarks,5,Introduction,Test generation is the bread-and-butter in VLSI Testing Efficient and powerful ATPG can alleviate high costs of DFT Goal: generation of a small set of effective vectors at a low computational cost ATPG is a very challenging task Exponential complexity Circuit sizes contin

4、ue to increase (Moores Law) Aggravate the complexity problem further Higher clock frequencies Need to test for both structural and delay defects,6,Conceptual View of ATPG,Generate an input vector that can distinguish the defect-free circuit from the hypothetically defective one,7,Fault Models,Instea

5、d of targeting specific defects, fault models are used to capture the logical effect of the underlying defect Fault models considered in this chapter: Stuck-at fault Bridging fault Transition fault Path-delay fault,8,Simple illustration of ATPG,Consider the fault d/1 in the defective circuit Need to

6、 distinguish the output of the defective circuit from the defect-free circuit Need: set d=0 in the defect-free circuit Need: propagate effect of fault to output Vector: abc=001 (output = 0/1),9,Example 1,10,A Typical ATPG System,Given a circuit and a fault model Repeat Generate a test for each undet

7、ected fault Drop all other faults detected by the test using a fault simulator Until all faults have been considered Note 1: a fault may be untestable, in which no test would be generated Note 2: an ATPG may abort on a fault if the resources needed exceed a preset limit,11,Category of ATPG,Simulatio

8、n-based Exhaustive Random-pattern generation Pseudo-random-pattern generation Path sensitization D-algorithm, 9-V algorithm PODEM, FAN TOPS, SOCRATES Boolean satisfiability Select a primitive D-cube of the fault to be the test cube; Put logic outputs with inputs labeled as D (D) onto the D-frontier;

9、 D-drive (); Consistency (); return ();,46,D-frontier,Fault Cone - Set of hardware affected by fault D-frontier Set of gates closest to POs with fault effect(s) at input(s),47,Singular Cover Example,Minimal set of logic signal assignments to show essential prime implicants of Karnaugh map,48,D-Cube

10、Operation of D-Intersection,49,Concluding Remarks,Covered a number of topics Theoretical Foundations Combinational & sequential ATPG Untestable fault identification Simulation-based & hybrid ATPG Delay testing Bridging fault testing Compaction, N-Detect, FSM testing Challenges Ahead Fast untestable fault identification essential to remove large numbers of stuck-at, bridge, delay faults Sequential ATPG remains an open research area,50,中科院研究生院課程:VLSI測試與可測試性設(shè)計,下次課預告 時間:2007年10月29日(周一7:00pm) 地點:S106室 內(nèi)容:測試生成(2) 教材:VLSI TEST PRINCIPLES AND ARCHITECTURES Chapter 4 Test Generation,51,

展開閱讀全文
溫馨提示:
1: 本站所有資源如無特殊說明,都需要本地電腦安裝OFFICE2007和PDF閱讀器。圖紙軟件為CAD,CAXA,PROE,UG,SolidWorks等.壓縮文件請下載最新的WinRAR軟件解壓。
2: 本站的文檔不包含任何第三方提供的附件圖紙等,如果需要附件,請聯(lián)系上傳者。文件的所有權(quán)益歸上傳用戶所有。
3.本站RAR壓縮包中若帶圖紙,網(wǎng)頁內(nèi)容里面會有圖紙預覽,若沒有圖紙預覽就沒有圖紙。
4. 未經(jīng)權(quán)益所有人同意不得將文件中的內(nèi)容挪作商業(yè)或盈利用途。
5. 裝配圖網(wǎng)僅提供信息存儲空間,僅對用戶上傳內(nèi)容的表現(xiàn)方式做保護處理,對用戶上傳分享的文檔內(nèi)容本身不做任何修改或編輯,并不能對任何下載內(nèi)容負責。
6. 下載文件中如有侵權(quán)或不適當內(nèi)容,請與我們聯(lián)系,我們立即糾正。
7. 本站不保證下載資源的準確性、安全性和完整性, 同時也不承擔用戶因使用這些下載資源對自己和他人造成任何形式的傷害或損失。

相關(guān)資源

更多
正為您匹配相似的精品文檔
關(guān)于我們 - 網(wǎng)站聲明 - 網(wǎng)站地圖 - 資源地圖 - 友情鏈接 - 網(wǎng)站客服 - 聯(lián)系我們

copyright@ 2023-2025  zhuangpeitu.com 裝配圖網(wǎng)版權(quán)所有   聯(lián)系電話:18123376007

備案號:ICP2024067431-1 川公網(wǎng)安備51140202000466號


本站為文檔C2C交易模式,即用戶上傳的文檔直接被用戶下載,本站只是中間服務(wù)平臺,本站所有文檔下載所得的收益歸上傳人(含作者)所有。裝配圖網(wǎng)僅提供信息存儲空間,僅對用戶上傳內(nèi)容的表現(xiàn)方式做保護處理,對上載內(nèi)容本身不做任何修改或編輯。若文檔所含內(nèi)容侵犯了您的版權(quán)或隱私,請立即通知裝配圖網(wǎng),我們立即給予刪除!