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module Dig_clk(
input CLK_50M,
input CLK_1HZ,
input CLK_1K,
input RSTN,
input selec,
input SET_add,
//input SET_sub,
output [23:0]time_value,
output [3:0]LED
);
wire CLK_1S;
wire [7:0]hour,min,sec;
assign LED = ~mode;
wire [3:0]mode;
set_time D1(
.RSTN(RS
2、TN),
.TURN(selec),
.flag(mode)
);
wire value0,value1,value2;
mode_sel D2(
.set_add(SET_add),
.CLK(CLK_1HZ),
.mode(mode[2]),
.value(value2)
);
wire CLK_min,CLK_h;
sec_bit D3(
.CLK_1S(value2),
.RSTN(RSTN),
.sec(sec),
.CLK_min(CLK_min)
);
mode_sel D4(
.set_add(SET_add),
.CLK(C
3、LK_min),
.mode(mode[1]),
.value(value1)
);
min_bit D5(
.CLK_min(value1),
.RSTN(RSTN),
.min(min),
.CLK_h(CLK_h)
);
mode_sel D6(
.set_add(SET_add),
.CLK(CLK_h),
.mode(mode[0]),
.value(value0)
);
hour_bit D7(
.CLK_h(value0),
.RSTN(RSTN),
.hour(hour),
);
assign time_value = hour
4、*10000+min*100+sec;
endmodule
module set_time (
input RSTN,
input TURN,
output reg[3:0]flag
);
always@(posedge TURN or negedge RSTN)
begin
if(~RSTN)
flag <= 4'b1000;
else
flag <= {flag[2:0],flag[3]};
end
endmodule
module mode_sel(
input CLK,
input set_add
5、,
input mode,
output value
);
assign value = (mode)?set_add:CLK;
endmodule
module sec_bit(
input CLK_1S,
input RSTN,
output reg[7:0]sec,
output reg CLK_min
);
always@(posedge CLK_1S or negedge RSTN)
begin
if(!RSTN)
sec <= 0;
else if(sec == 8'd59)
begin
sec <= 0;
C
6、LK_min <= 1;
end
else
begin
sec <= sec + 1;
CLK_min <= 0;
end
end
endmodule
module min_bit(
input CLK_min,
input RSTN,
output reg[7:0]min,
output reg CLK_h
);
always@(posedge CLK_min or negedge RSTN)
begin
if(!RSTN)
min <= 0;
else if(min == 8'd59 )
begin
min <=
7、0;
CLK_h <= 1;
end
else
begin
min <= min + 1;
CLK_h <= 0;
end
end
endmodule
module hour_bit(
input CLK_h,
input RSTN,
output reg[7:0]hour
);
always@(posedge CLK_h or negedge RSTN)
begin
if(!RSTN)
hour <= 0;
else if(hour ==8'd23)
hour <= 0;
else
hour <= h
8、our + 1;
end
endmodule
module lab4_top(
input CLK_50M,
input RSTN,
//input mode,
//input [23:0]num_out,
output wire[2:0]sel_out,
output wire[7:0]seg,
output [3:0]LED,
input TURN,
input SET_add
//input SET_sub
);
wire CLK_1HZ;
wire CLK_1KHZ;
wire [23:0]num_out;
//wire [3:0
9、]data_num;
wire [23:0]time_value;
wire [23:0]num_value;
sys_clk U1(
.CLK(CLK_50M),
.RSTN(RSTN),
.CLK_1K(CLK_1KHZ),
.CLK_1HZ(CLK_1HZ)
);
seg_Display U2(
.CLK_1K(CLK_1KHZ),
.RSTN(RSTN),
.num_value(time_value),
.sel(sel_out),
.seg(seg)
);
wire turn, set_add;
key_esk #(2)U3(
.C
10、LK_1K(CLK_1KHZ),
.key_in({TURN,SET_add}),
.key_out({turn,set_add})
);
Dig_clk U6(
.CLK_50M(CLK_50M),
.CLK_1HZ(CLK_1HZ),
.CLK_1K(CLK_1KHZ),
.RSTN(RSTN),
.selec(turn),
.SET_add(set_add),
//.SET_sub(SET_sub),
.time_value(time_value),
.LED(LED)
);
Endmodule
module key_esk(
input CLK_1K,
input [width-1:0]key_in,
output [width-1:0]key_out
);
parameter width = 3;
reg [width:0]key1,key2,key3;
assign key_out = ~(key1|key2|key3);
always@(posedge CLK_1K)
begin
key1 <= key_in;
key2 <= key1;
key3 <= key2;
end
endmodule
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基于FPGAverilog數(shù)字鐘源碼(共6頁(yè))
