813 右軸承座組件工藝及夾具設計
813 右軸承座組件工藝及夾具設計,軸承,組件,工藝,夾具,設計
無錫職業(yè)技術學院畢業(yè)設計說明書I錫林右軸承座組件工藝及夾具設計摘要:錫林結(jié)合體是梳棉機上的一個關鍵零部件,它的加工質(zhì)量直接影響到梳棉機的工作穩(wěn)定性,使用壽命等性能。因此其加工精度要求較高,尤其是軸承蓋與軸承座的結(jié)合面及軸承孔的精度有很高的要求,這些精度的保證是本工藝規(guī)程的難點,同時也是重點。本次設計針對錫林結(jié)合體的自身特點及生產(chǎn)廠家現(xiàn)有的設備來編制工藝規(guī)程及相關專用夾具的設計。內(nèi)容主要包括:毛坯的確定、定位基準的選擇、工序余量確定等。關鍵詞:軸承結(jié)合體 工藝規(guī)程 專用夾具xilin right bearing block discreteness crafts and grip designAbstract: The Xilin bearing combine is an important part of the card . Its machining quantity affects the working stability and the service life of the card. So it machining accuracy have higher request. Particularly the combine face of the bearings cover and the bearing body andthe bearings bore have the very high request. The assurance of these accuracies is the keytechnique and difference of this process rules. To preferring the characteristics of he connecting rod of the United States races car and the condition of the machining etc, this craft rules are well designed. The contents mainly includes: the semi-finished product really settles, the choice of the fixed position basis, the part preface remaining measure assurance etc.Key words: bearing combine machining rules clamp無錫職業(yè)技術學院畢業(yè)設計說明書II目 錄第一章 引言 11.1 高產(chǎn)梳棉機在線自動監(jiān)控監(jiān)測技術的發(fā)展 11.2 梳棉機除塵技術的發(fā)展 21.3 梳棉機上電子剎車技術的發(fā)展 31.4 21 世紀高產(chǎn)梳棉機的新發(fā)展4第二章 錫林右軸承座組件工藝 102.1 零件(即錫林結(jié)合體)分析 102.1.1 功用及工作狀態(tài) 102.1.2 零件結(jié)構(gòu)特點 102.1.3 零件材料的材料分析 102.1.4 零件主要表面要求 122.1.5 工藝分析 122.2 零件工藝路制定 132.2.1 毛坯種類的選擇 132.2.2 定位基準的選擇 142.2.3 加工方法的選擇 152.2.4 加工工序的確定方案 162.2.5 工藝路線方案比較 182.2.6 工序的安排及作用 202.2.7 重點工序分析 212.2.8 加工余量的確定 222.2.9 確定切削用量 24第三章 對應的夾具設計 283.1 夾具的選用 28311 鉆床夾具的主要類型 28312 鉆模 28313 鏜夾具 293.2 夾具設計要求 303.3 確定方案 31331 定位方案的確定 31332 夾緊方案的確定 32無錫職業(yè)技術學院畢業(yè)設計說明書III333 夾具的裝配總圖 34334 夾具的驗證 34335 夾具的制造的注意事項 36336 夾具的經(jīng)濟分析 373.4 鉆孔安裝使用說明 39致謝 40參考文獻 41畢業(yè)設計調(diào)研報告- 1 -調(diào)研報告高產(chǎn)梳棉機是 20 世紀后期發(fā)展起來的,不論梳理技術、自動監(jiān)控技術、在線檢測技術、負壓吸塵技術以及安全生產(chǎn)技術都有了很大的發(fā)展,車速日益增高,產(chǎn)量一再增,尤其是產(chǎn)品質(zhì)量有了明顯的進步,生條結(jié)雜少,重量不勻率低,為紡好紗織也布奠定了堅實的基礎。從 1999 年法國巴黎國際紡織機械展覽會及 2000 年 10 月美國格林威爾國際紡織機械展覽會上可以看出新型高產(chǎn)梳棉機具有以下特征: (1)車速高,錫林速度在 600r/min 左右,克魯斯羅爾 MK5 直徑為 40 公分小錫林則高達770r/min。 (2)在新型針布應用的基礎上又增加了在線蓋板、錫林隔距調(diào)整及在線磨針技術,如:DK903、瑞士 C51 高產(chǎn)梳棉機。 (3)在線檢測技術及自動監(jiān)控技術的發(fā)展,如自調(diào)勻整、在線監(jiān)測棉結(jié)、檢測各部運轉(zhuǎn)速、產(chǎn)量等數(shù)據(jù)并及時進行熒屏顯示等。 (4)喂入部分三刺輥技術的應用改進了開松、除雜、減輕主梳理、除雜負擔,為錫林增速創(chuàng)造了條件。 (5)負壓吸塵體系的形成,使高速回轉(zhuǎn)的梳棉機凈化水平提高,也是梳棉機高速高產(chǎn)的保證。 (6)應用變頻調(diào)速技術,使一些主要回轉(zhuǎn)部件能單獨傳動,并以電子技術控制相互的速比。 (7)安全防護措施的改善,如高速回轉(zhuǎn)的錫林重量為 1.5 噸,可在 60s 內(nèi)剎車停止運行等。機上安全門罩都裝有電子鎖,只有機器停穩(wěn)后才能開啟。最新型高速高產(chǎn)梳棉機將傳動與調(diào)節(jié)分別設在機器左右兩側(cè), ,有些技術參數(shù)可在線調(diào)節(jié),使安全生產(chǎn)得到保障.而且減少了停臺. 1、關于新型針布的開發(fā)與應用 1.1 20 世紀后 30 年國內(nèi)外新型針布的開發(fā)與應用取得很大發(fā)展,如瑞士 Graf 公司的錫林、蓋板、道夫針布、刺輥鋸條都成套生產(chǎn)。英國 ECC、德國 Holl、日本金井、瑞典 ABK、美國HW 等公司的針布也占有一定市場。一搬認為 Graf 針布較好。國內(nèi)青島紡機廠、上海金屬針布廠引進 Graf 生產(chǎn)線生產(chǎn)的針布性能較好,無錫、天津、常州、南通等均有生產(chǎn)新型針布的工廠。在梳理技術中應用新型針布、增加固定蓋板、提高錫林位置、蓋板踵趾差由0.90mm 減為 0.56mm 和蓋板反向回轉(zhuǎn)等措施對增加梳理度、減少生條結(jié)雜作用明顯。其中新型針布的應用及配套是重要因素。 假如其他條件不變,只配套使用新型針布,降低結(jié)雜效果也是顯著的。 梳棉是降低生條棉結(jié)含量最有效的工序,生條棉結(jié)可降到 80 粒/克,為喂入棉絮中棉結(jié)畢業(yè)設計調(diào)研報告- 2 -量的 20%,正常情況下若用新型針布,梳棉機械設備安裝維護精細,各部工藝,隔距及速比符合工藝要求,成紗棉結(jié)還可減少 30%-40%。 1.2 除搞好梳棉機針布配套外,針布保養(yǎng)維護十分重要。國外一些先進的高產(chǎn)梳棉機臺DK903、C51、MK5C 等對機械設備精度要求很高,有的錫林是鋼板卷制后進行精加工、動平衡、消除內(nèi)應力,徑向跳動要求達到 0.03mm 以下。在 DK903、C51 上還配備了精調(diào)蓋板錫林隔距及在線自動磨針體系(自動磨錫林、蓋板),蓋板隔距調(diào)整精度很高。自動磨蓋板即磨針尖又磨側(cè)面,使其保持原有針的鋒銳外形。 一般錫林蓋板針布生產(chǎn)加工 2001000 噸原料后要更換,實行在線磨針后即保持產(chǎn)品質(zhì)量的穩(wěn)定,還可延長針布使用壽命 10%20%。 1.3 新型針布的設計及選用針對性強,金屬針布廠根據(jù)纖維種類、長度、細度、含雜、單強、梳棉機的產(chǎn)量、錫林速度、生條定量、紡紗號數(shù)、純棉、化纖混紡及一些特種紗線,設計了許多種類的針布:如高產(chǎn)梳棉機針布、高支紗針布、低級原棉針布、普通棉型針布、棉型化纖針布、中長化纖針布及細旦、超細旦針布等不同系列的新型針布,為了進行合理配套使針布發(fā)揮更好作用,不僅有錫林蓋板各系列的新型針布,而且道夫針布、刺輥齒條也有相應的規(guī)格型號。 1.4 新型針布在國內(nèi)應用以來使生條質(zhì)量、成紗質(zhì)量大大提高,棉條結(jié)雜降低,但也帶來一些困難,尤其在商品經(jīng)濟時代,市場的需要使紡織企業(yè)品種翻改頻率很高,企業(yè)在許多情況下不能正確對號使用針布,造成針布使用的混亂,不能很好發(fā)揮新型針布的作用。國內(nèi)大連工學院與重慶紡織器材廠聯(lián)合開發(fā)了“通用型金屬針布”。其中針布工作角的設計兼顧化纖與棉花的要求,適應性比較靈活,在一定程度上可適當滿足翻改品種的需要。 2、錫林速度的技術改進 20 世紀末梳棉機錫林速度加快作為提高梳理效果的主要手段,錫林加速后梳棉機有如下特點: 21 林表面速度及離心力提高,排雜能力加強,據(jù)測,錫林速度由 300r/min 提高到600r/min 時,生條結(jié)雜減少 50%左右。 22 錫林上的分梳負荷因錫林速度的提高而降低,對提高分梳質(zhì)量有利。 23 單產(chǎn)水平與錫林速度及針布對纖維梳理能力之間不成比例,當單產(chǎn)水平增加 10 倍(由10gk 增回到 100gk),錫林速度僅提高 3 倍。對纖維的分離能力也只增加 3 倍。 24 錫林速度與梳理力之間也不成比例,據(jù)測:錫林速度由 300r/min 提高到 600r/min,梳理力只增加 10%20%。 25 錫林速度的增加既有對纖維梳理開松及除雜功能的有利因素,但也有使纖維應力增加的不利因素,因此要兼顧平衡兩者之間的關系。 畢業(yè)設計調(diào)研報告- 3 -26 錫林速度提高時要認真考慮刺輥速度的設計,因為當棉層喂入刺輥的纖維受握持分流作用、增加除雜的同時纖維受到損傷使短絨增加,因此在錫林速度提高后要適當考慮與刺輥的速比,也就是說刺輥速度應該受到一定程度工藝性的制約。 27 錫林與蓋板間是主分梳區(qū),由于不是握持梳理,因此在錫林加速后與蓋板間速比可保持不變。即蓋板速度相應提高有利充分排除疵點。 28 隨著梳棉機各項配套技術的發(fā)展和精度的進一步提高,估計梳棉機錫林速度還會進一步提高,以滿足更高產(chǎn)量的要求。 3、蓋板速度對改善梳理、降低棉結(jié)的作用: 近 20 年來梳棉機的夕林速度已高達 600 轉(zhuǎn)/分,有的甚至更高,相對應的蓋板速度在采取了許多措施后,相應提高了蓋板速度,調(diào)整了夕林與蓋板之間的速比,像 DK903 高產(chǎn)梳棉機的蓋板骨,由鋁合金材料制成,即輕又牢,兩邊由兩組齒形帶連接傳動,蓋板骨沿著塑料軌道滑動,MK5 型梳棉機每根蓋板兩側(cè)是由球面軸承支持在曲軌上運行,運轉(zhuǎn)速度可大大提高。普通梳棉機蓋板速度一般都在 100-400 毫米/分。經(jīng)過新型蓋板及傳動的改進,使蓋板速度提高到 1200 毫米/分,蓋板的梳理作用大大提高。在高產(chǎn)梳棉機上,夕林速度 600 車/分,蓋板速度 1200 毫米/分時,對提高梳理度、增加轉(zhuǎn)移、減少結(jié)雜有明顯作用。為適應夕林速度提高,相應提高蓋板速度,保持相互間的速比,有利減少棉結(jié)、排除雜質(zhì)。 4、三刺輥開松除雜系統(tǒng)的討論 為了提高梳棉機的產(chǎn)質(zhì)量,德國成功地推出了擁有三刺輥系統(tǒng)的 DK803、DK903 高產(chǎn)梳棉機。這種三刺輥系統(tǒng)具有獨特的內(nèi)涵。 三刺輥直徑小,均為 172.5mm,一般單刺輥直徑為 250mm、傳統(tǒng)多刺輥直徑為 248350mm。刺輥直徑愈小,迥轉(zhuǎn)速度愈快,其分離和梳理纖維的效果愈好。這樣可使分梳線速度下降(尤其第一刺輥),從而減少對纖維的打擊力,保持纖維不受損傷。同時由于離心力加大,有利于雜質(zhì)的去除。錫林與刺輥間線速度進一步提高。 第一刺輥有梳針加工纖維時其作用使纖維在最小損傷狀態(tài)下被開松、分梳。 DK 系列三刺輥系統(tǒng)針齒間的配置與精細開棉機 CVT3 一樣,均為剝?nèi)∨渲?。齒密逐只加大,如紡超細旦纖維時其三刺輥之間的密度配置分別為 32、161、205 齒(25.4mm2)。工作角逐漸變小,速度逐漸變快,實現(xiàn)了漸增性開松與除雜。 在三刺輥系統(tǒng)中每個刺輥配有一塊分梳板、除塵刀和負壓吸口以幫助進一步除雜,這種新型三刺輥系統(tǒng)清除棉結(jié)功能比以前有所提高,在一定程度減輕了錫林蓋板工作分梳區(qū)負擔。配置除雜吸口是三刺輥系統(tǒng)取得成功的組成部分,可緩解高速刺輥迥轉(zhuǎn)時所帶動的氣流在刺輥周圍產(chǎn)生高壓,從而造成氣流運動紊亂,影響纖維分梳和除雜。 DK 系列三刺輥系統(tǒng)的最大優(yōu)點在于:它喂給錫林一蓋板工作區(qū)的是一個均勻、精細、開松畢業(yè)設計調(diào)研報告- 4 -良好的纖維網(wǎng)。在這個纖維網(wǎng)中,纖維基本上是以分離狀態(tài)存在的。將 DK903 與 DK760(傳統(tǒng)單刺輥)相比較,紗疵總數(shù)可減少 50%,梳棉機產(chǎn)量可增加 50%90%。 三刺輥開松、梳理及除雜體系是開清棉任務在梳棉機的延伸,并擔負著梳棉機的預梳理任務以上是現(xiàn)代梳棉機梳理技術的餓發(fā)展,不過從我國紡織經(jīng)濟的發(fā)展來看梳棉機將趨向“三高”:清梳聯(lián)技術的迅速發(fā)展對梳棉機提出了更高的要求,清梳聯(lián)的發(fā)展推動了梳棉機的技術進步,梳棉機的技術進步又促進了清梳聯(lián)的推廣與普及。清梳聯(lián)生產(chǎn)線配套的梳棉機應具有“三高”功能,即高速、高產(chǎn)、高質(zhì)量。目前國際上最高產(chǎn)量可達到 140 公斤/臺/小時。 國產(chǎn)梳棉機通過消化吸收國外先進技術,其設計水平大大提高,基本上達到國際水平,但其制造精度與國外先進水平相比仍然存在著差距。另外,使用廠家對國產(chǎn)梳棉機的認可度不如國際著名公司高,主要體現(xiàn)在實際產(chǎn)量與設計產(chǎn)量的差距仍然較大。盡管如此,國產(chǎn)梳棉機的技術進步仍然得到行業(yè)內(nèi)外的肯定。國內(nèi)外高產(chǎn)梳棉機具有以下共同特點: 梳棉提高產(chǎn)量。Truetzschler 公司的 DK903 型梳棉機最高產(chǎn)量 140 公斤/臺/ 小時,Rieter公司的 C51 型、 Marzoli 公司的 C501 型梳棉機產(chǎn)量均為 120 公斤/臺/ 小時,國內(nèi)的 FA225 型、FA232 型等機型均達 100 公斤/臺/小時。 錫林軸承結(jié)合件是 A186D 型梳棉機上的錫林支承件,雖然由于錫林軸承件伴隨錫林旋轉(zhuǎn)工作,又是錫林筒的支承件,因此它對于錫林與錫林墻板的同軸度、軸向壓力、機件的磨損 、及錫林周圍機件安裝的準確性和錫林的回轉(zhuǎn)平穩(wěn)度都有不可忽視的影響,這也就影響到梳棉機的生產(chǎn)效率以及影響企業(yè)的經(jīng)濟發(fā)展,所以本人的理論設計對梳棉機的改進具有一定的參照意義,更加展望從錫林部件方面著手研究對梳棉機的生產(chǎn)有新的突破,從而使中國紡織經(jīng)濟達到更強。外文翻譯資料1單片集成 MEMS 技術在過去的 20 年中,CMOS 技術已成為集成電路主要制造工藝,制造成本下降的同時,成品率和產(chǎn)量也得到很大提高,COMS 工藝將繼續(xù)以增加集成度和減小特制尺寸向前發(fā)展。當今,CMOS 集成工藝不僅被利用在集成電路設計上,而且,也被利用在很多微傳感器和微執(zhí)行器上,這樣可以把微傳感器與集成電路集成在一起,構(gòu)成功能強大的智能傳感器。隨著微傳感應用范圍的不斷擴大,對傳感器的要求也越來越高,對未來微傳感器的主要要求是:微型化和集成化;低功耗和低成本;高精度和長壽命;多功能和智能化。硅微機械和集成電路的一體化集成,可以滿足上述要求。目前,集成傳感器的產(chǎn)品多數(shù)采用混合集成,單片集成的比例很小。而實現(xiàn)單片集成是實現(xiàn)傳感器智能化的關鍵,特別是單片集成 MEMS 傳感器技術也是當今片上系統(tǒng)芯片能否實現(xiàn)的關鍵技術之一。可見,對各種單片集成 MEMS 技術難點進行分析以及給出目前已有的各種單片集成 MEMS 技術是非常必要的。1.單片集成 MEMS 技術的優(yōu)勢和面臨的挑戰(zhàn)實現(xiàn) MEMS 和 CMOS 共同工作是分別制造 MEMS 傳感器和 CMOS 集成電路,然后,從各自的晶片切開,固定在一個共同的襯底上,并且,連線鍵合,這樣就實現(xiàn)兩者的集成,這就是所謂的混合(hybrid)方法。這種方法不會產(chǎn)生 MEMS 制造過程對 CMOS 電路的污染,同時,兩者生產(chǎn)過程互不干擾。但是,由于信號經(jīng)過鍵合點和引線,導致在高頻應用時,信號傳輸質(zhì)量下降,并且,開發(fā)兩套生產(chǎn)線增加了產(chǎn)品的成本。為了解決一些性能問題,并降低制造成本,提出把 MEMS 部分做在和 CMOS 電路同一塊襯底上,也就是產(chǎn)生了與 CMOS 工藝兼容單片集成 MEMS 技術或叫 CMOS-MEMS 技術。這種方法相對混合方法總的來說有如下優(yōu)勢:第一,性能能得到很大的提高,因為寄生電容和串擾現(xiàn)象可以顯著減小;第二,混合方法需要復雜的封裝技術以減小傳感器接口的影響,而單片集成方法需要的封裝技術相對簡單,所以,降低傳感器成本;第三,單片集成傳感器技術也是陣列傳感器的需要,是克服陣列傳感器與外圍譯碼電路互連瓶頸的一種有效方法;第四,開發(fā)單片集成 MEMS 產(chǎn)品比開發(fā)混合 MEMS 產(chǎn)品所需的時間短,而且,開發(fā)成本低。單片集成 MEMS 技術根據(jù) MEMS 器件部分與 CMOS 電路部分加工順序不同可以分為前CMOS(pre-CMOS)、混合 CMOS(intermediate-CMOS)及后 CMOS(post-CMOS)集成方法。post-CMOS 方法是在加工完 CMOS 電路的硅片上,通過一些附加 MEMS 微細加工技術以實現(xiàn)單片集成 MEMS 系統(tǒng),目前,單片集成 MEMS 技術主要以這種方法為主。post-CMOS 方法主要問題是 MEMS 加工工藝溫度會對前面的 CMOS 電路性能產(chǎn)生影響,更為嚴重的是后面高溫MEMS 加工工藝溫度與前面 CMOS 工藝金屬化不兼容。以目前研究最多的多晶硅作為結(jié)構(gòu)層的MEMS 為例,使磷硅玻璃致密化退火溫度為 950,而使作為結(jié)構(gòu)層多晶硅的應力退火溫度則達到 1050,這將使 CMOS 器件結(jié)深發(fā)生遷移。特別是 800時淺結(jié)器件的結(jié)深遷移就會影外文翻譯資料2響器件的性能。另一方面,采用常規(guī)鋁金屬化工藝時,當溫度達到 400-450時,CMOS 電路可靠性將受到嚴重的影響。從以上可以看出:如何克服后面高溫 MEMS 微結(jié)構(gòu)加工溫度對前面的已加工完的 CMOS 電路影響是解決單片集成 MEMS 系統(tǒng)關鍵所在。目前,國際上解決這個問題基本是通過 3 種方式:第一種是以難熔金屬化互連代替鋁金屬化互連,如,伯克利大學的以鎢代替鋁金屬互連方案,這樣提高容忍后續(xù)加工 MEMS 所需的高溫;第二種方式是通過尋找低制作溫度且機械性能優(yōu)良的材料代替多晶硅作為結(jié)構(gòu)層材料;第三種方式是利用CMOS 本身已有結(jié)構(gòu)層作為 MEMS 結(jié)構(gòu)層。pre-CMOS 集成方法是先制造 MEMS 結(jié)構(gòu)后制造 CMOS 電路,這種集成 CMOS 技術雖然克服post-CMOS 方法中 MEMS 高溫工藝對 CMOS 電路的影響,但由于存在垂直的微結(jié)構(gòu),所以,存在傳感器與電路互連臺階覆蓋性問題,而且,在 CMOS 電路工藝過程中對微結(jié)構(gòu)的保護也是一個需要考慮的問題。甚至已優(yōu)化微調(diào)的 CMOS 工藝流程,例如:柵氧化可能被重摻雜的結(jié)構(gòu)層影響。另外,MEMS 工藝過程中不能有任何的金屬或其他的材料,如壓電材料聚合物等,使得這種方法只適合一些特殊應用。intermediate-CMOS 是在 CMOS 電路生產(chǎn)過程中插入一些 MEMS 微細加工工藝來實現(xiàn)單片集成 MEMS 的方法。這種方法已很成熟,并已有很多商品化產(chǎn)品,也是研究最早一種單片集成方法,是解決 pre-CMOS 和 post-CMOS 方法存在問題有效方法,但是,由于需要對現(xiàn)有的標準 CMOS 或 BiCMOS 工藝進行較大的修改,因此,這種方法的使用有一定限制。2.單片集成 MEMS 的主要技術現(xiàn)狀目前,單片集成 MEMS 技術主要以 post-CMOS 技術為主,通過一系列的與 CMOS 工藝兼容的表面微細加工和體加工實現(xiàn)單片集成 MEMS。又可分為 2 種:一種是在 CMOS 結(jié)構(gòu)層上面再淀積一層結(jié)構(gòu)層的微加工;另一種是直接以 CMOS 原有的結(jié)構(gòu)層作為 MEMS 結(jié)構(gòu)層的微加工。2.1 淀積新的結(jié)構(gòu)材料作 MEMS 結(jié)構(gòu)的集成技術2.1.1 多晶硅作為結(jié)構(gòu)層的集成表面微細加工技術這種工藝典型代表是伯克利大學開發(fā)模塊集成 CMOS 與 MEMS 工藝(modular integration of CMOS with micro-structures,MICS),這種方法是以多晶硅為微結(jié)構(gòu)層,磷硅玻璃(PSG)作為犧牲層的表面微細加工技術。采用難熔金屬鎢的金屬化互連代替鋁金屬化互連以承受后面的生產(chǎn)多晶硅微結(jié)構(gòu)所需要的高溫,但是,在 600時,鎢容易與硅形成反應,伯克利大學是通過在接觸孔上放一層 TiN 阻擋層來解決這一問題的。MICS 工藝基本流程是:完成鎢金屬化的 CMOS 工藝后,淀積 30010-10nm 低溫氧化物(LTO),然后,低壓化學氣相淀積 20010-10nm 的氮化硅薄膜保護已生產(chǎn)的 CMOS 電路,腐蝕完微結(jié)構(gòu)與CMOS 電路的接觸孔后,淀積第 1 層現(xiàn)場摻雜多晶硅(35010-10)作為 CMOS 電路與微結(jié)構(gòu)的互連線,再在上面淀積 1um 厚的 PSG 作為犧牲層以及淀積厚度為 2um 多晶硅結(jié)構(gòu)層。通過外文翻譯資料3在第 2 層多晶硅上再淀積一層 0.5um 的 PSG,以及在氮氣環(huán)境下的 1000快速退火 1min 來降低作為結(jié)構(gòu)層的多晶硅應力。最后,刻蝕多晶硅結(jié)構(gòu)圖形以及腐蝕掉其下面的犧牲層(PSG)以釋放微結(jié)構(gòu)。2.1.2 以其他材料作結(jié)構(gòu)層集成表面微細加工技術多晶硅鍺不僅有與多晶硅相似的優(yōu)良機械性能,而且,淀積溫度低與 CMOS 工藝兼容,所以,目前被廣泛研究。伯克利大學開發(fā)的基于硅鍺結(jié)構(gòu)層的工藝與 MICS 工藝基本相似。主要技術革新:第一,保護層采用不同的材料,以前 MICS 工藝采用 835的 LPCVD 氮化硅,而現(xiàn)在則是采用兩層 LTO 和中間夾一層不定型硅(a-Si)作為 CMOS 電路保護層,其中,a-Si 分兩步淀積,第一步淀積在 450;第二步淀積則在 410,這樣溫度是不會損壞鋁金屬化 CMOS 電路;第二,采用低淀積溫度多晶硅鍺作為結(jié)構(gòu)層材料,其低壓化學氣相淀積(LPCVD)溫度只有 400,采用快速退火溫度也僅為 550,時間為 30s。而 MICS 工藝淀積多晶硅結(jié)構(gòu)溫度則超過 600。從以上兩點可知,由于整個后續(xù) MEMS 加工溫度不超過450,所以,不會對鋁金屬化互連 CMOS 電路產(chǎn)生很大的影響。采用鋁作為結(jié)構(gòu)層材料也會獲得很大成功,最為成功的是德州儀器開發(fā)低溫表面微細加工技術,并用這種技術成功生產(chǎn)了數(shù)字微鏡設備(DMD)。技術革新主要表現(xiàn)在采用濺射鋁作為結(jié)構(gòu)層材料,并且,采用光致抗蝕劑作為犧牲層,這種低溫后處理使得已生產(chǎn)的下面SRAM 單元不被破壞 。鋯鈦酸鉛(PZT)電材料因具有優(yōu)良的壓電性能、熱釋電性能、鐵電性能和介電性能而被廣泛應用在鐵電存儲器中以及作為高介質(zhì)材料。同時,還可以利用鋯鈦酸鉛壓電效應制作微傳感器以及微執(zhí)行器。PZT 薄膜工藝與硅集成工藝兼容,如,目前的基于金屬有機化學氣相淀積(OCVD)方法制作 PZT 薄膜溫度已降低到 43075,這個溫度還在降低,因此,采用這種材料作為結(jié)構(gòu)層是很有希望與 CMOS 工藝集成的。2.2 以原 CMOS 結(jié)構(gòu)層作 MEMS 結(jié)構(gòu)的集成技術2.2.1 犧牲鋁的微加工技術如果 CMOS 金屬化合物用作犧牲材料,則可能存在和 CMOS 工藝完全兼容的表面微細加工丁藝,這種方法被稱作犧牲鋁蝕刻(sacrificial aluminum etching,SALE)。在許多CMOS 工藝過程中,都采用了兩層由鋁合金構(gòu)成的金屬層。第 1 層金屬作為犧牲層被清除,可以制造出電介質(zhì)金屬化合物;第 2 層由金屬和鈍化物組成,第 2 層金屬介于兩個電介質(zhì)之間,適當結(jié)構(gòu)化后,便可以作為反射鏡、電極、熱電阻或電熱調(diào)節(jié)器。其基本工藝過程包括:(1)保護電氣連接觸點不受到蝕刻;(2)腐蝕犧牲鋁層;(3)涮洗清除徼結(jié)構(gòu)里面的蝕刻劑;(4)烘干微機構(gòu)。2.2.2 單晶體硅活化蝕刻和金屬化法外文翻譯資料4單體硅活化蝕刻和金屬化法(single crystal reactiveetching and metallization,SCREAM)可用于制造,梁、橋這樣的結(jié)構(gòu),甚至可以用單晶硅制造更復雜的結(jié)構(gòu)。這種方法始于制造完的 CMOS 電路硅片,首先,淀積一層覆蓋接觸孔的氧化硅,這層氧化物保護 CMOS 電路免受后面工藝影響,并通過反應離子蝕刻(RIE)圖形化這層氧化物遮蔽層;然后,RIE 蝕刻硅溝槽,深度可達到 10um,氧化硅薄膜淀積下來,覆蓋在側(cè)面和水平面上。通過反應離子蝕刻掉水平面上的氧化物,而使豎直面受到保護,第二次反應離子蝕刻硅;最后,各向同性蝕刻硅,釋放出懸浮的微結(jié)構(gòu),同時,蝕刻接觸孔氧化物,并濺射金屬,這層金屬化淀積物使大縱橫比的粱變成電容性元素,用厚的抗蝕劑作掩蔽模圖形化金屬層。由于 SCREAM 的每一步均在低于 300的溫度下進行的,因此,是與 CMOS 電路兼容的。2.2.3 大縱橫比的 CMOS-MEMS 工藝Gamegle Melloa 大學開發(fā)的與 CMOS 兼容干法蝕刻方法,它應用各向同性硅蝕刻產(chǎn)生絕緣薄膜,CMOS 介質(zhì)和金屬化層在這個工藝中不僅用作金屬互連,而且,還作為微機械結(jié)構(gòu)尾。基本工藝過程為:首先,標準的 CMOS 工藝采用三層金屬 0.5upmN 阱工藝實現(xiàn);其次,金屬層 1 和 2 被用作電活性層,而第 3 層作為微機械加工的蝕刻掩模。應用化合物CHF3O2 的反應離子蝕刻(RIE),使整個芯片上的鈍化層被清除掉,在第 3 層金屬斷開區(qū)域,CMOS 薄膜夾層被一直蝕刻至基底,而上面覆蓋有第 3 層金屬的 CMOS 薄膜夾層則保留完好;最后,采用 SP6O2 等離子在不蝕刻微結(jié)構(gòu)側(cè)壁情況下各向同性蝕刻硅襯底。狹窄的絕緣層和導電層融為一體制造出梁和橋,例如:梳狀驅(qū)動器這樣的微結(jié)構(gòu)。2.2.4 體加工 CMOS-MEMS 工藝主要是通過蝕刻硅襯底等體加工技術來形成所需的 MEMS 結(jié)構(gòu),這種技術主要以蘇黎世大學為主??梢詮恼嫖g刻硅襯底,也可以從反面蝕刻硅襯底,利用各向異性腐蝕(100)方向的特性,從硅的正面蝕刻是可以得到未封閉的微結(jié)構(gòu),如,梁和支撐膜等,可選用的蝕刻劑可以是氫氧化四甲基銨水溶液(TMATH)或乙烯二胺溶液(EDP)。通過從已完成的硅片背部蝕該硅片可以得到封閉的介電薄膜,需要一個額外的掩模定義膜片的大小,通常采用的燭刻劑是 KOH。采用 XeF2 干法蝕刻的 post-CMOS 工藝也得到很大的發(fā)展。XeP2 是一種各向異性硅蝕刻劑,蝕刻速度很高,它是惰性氣體氙的一種稀有化合物。XeP2 既不蝕刻 IC 絕緣層,也不蝕刻鋁合金金屬化合物,因此,和 CMOS 完全兼容。經(jīng)過適當?shù)膮^(qū)域設計、連接和加掩模,在指定部位打開絕緣層,使基底硅局部暴露給蝕刻劑。因為 XeF2 即不蝕刻陶瓷,也不蝕刻塑料,從而適合集成 CMOS 微系統(tǒng)的微加工。使用這種方法可在已完成的 CMOS 芯片上無掩模蝕刻出微機構(gòu)。3.發(fā)展趨勢外文翻譯資料5單片集成 MEMS 技術已開發(fā) 10 多年了,已得到了迅猛發(fā)展,也涌現(xiàn)出各種 MEMS 制造服務組織和企業(yè),從而可以獲得一些組織或直接由特殊集成電路制造商提供 MEMS 加工。代表微系統(tǒng) IC 技術發(fā)展方向的組織包括美國的 MOSIS.Europractice 和歐洲的 TIMACMP;美國北卡羅納州的 Croons 集成微系統(tǒng)公司除了提供基本的 CMOS 工藝以外,還提供體微加工和表面徽加工、LIGA 工藝以及多用戶微機電系統(tǒng)工藝等;美國桑迪亞國家實驗室開發(fā)的超平面多層多晶硅工藝也已商品化;在歐洲從事特殊應用集成電路制造技術研究的包括奧地利微系統(tǒng)公司和瑞士的 EM 微電子公司。還有很多基于傳感器的特殊硅工藝也已經(jīng)被研究出來,如,德國的羅伯特博施公司和挪威的 SensoNor 公司等。從目前來看,集成 MEMS 技術將有如下趨勢:(1)post-CMOS 集成方法仍將是未來的主要開發(fā)技術,并將現(xiàn)有實驗室已開發(fā)的各種post-CMOS 單片集成 MEMS 技術產(chǎn)業(yè)化;(2)在集成 MEMS 系統(tǒng)上集成更多的復雜的電路包括數(shù)字接口和微控制器,這樣得到功能更強大、價格便宜的智能系統(tǒng);(3)開發(fā)封裝技術保護 CMOS 芯片免受環(huán)境的影響,不僅需要開發(fā)適應 MEMS 集成系統(tǒng)的封裝,而且,也需要開發(fā)能適應封裝的單片 MEMS 集成技術。4.結(jié)束語單片集成 MEMS 是實現(xiàn)智能傳感器的關鍵,也是 IC 業(yè)發(fā)展的一個重要方向。雖然目前各種方法都還存在一些問題,但是,隨著對其不斷的研究與 CMOS 工藝兼容性各種問題也會一一解決。本文對單片集成 MEMS 技術對工藝提出的要求進行了討論,并對目前各種單片集成MEMS 技術特點、工藝流程進行了介紹,同時,還給出未來單片集成 MEMS 技術未來發(fā)展趨勢。外文翻譯資料1Monolithically integrated MEMS technologyIn the past 20 years, CMOS technology has become a major integrated circuit manufacturing technology, manufacturing costs decline at the same time, yield and production has also been greatly improved, COMS technology will continue to increase integration and reduce development of a special size. Today, CMOS integrated process not only be used in the design of integrated circuits, but also to be used in many micro-sensors and micro-actuator, so it can be integrated circuits and micro-sensor integrated with a powerful, intelligent sensors. With micro-sensor constantly expanding the scope of application of the sensor increasingly high demands of the future microsensor the main requirements are: miniaturization and integration of low-power and low-cost high-precision and long life; - and intelligent. Micromachined silicon integrated circuits and the integration of integration, to meet the above-mentioned requirements. At present, the majority of products integrated sensor using hybrid integrated, monolithic integration of a very small percentage. And the realization of single-chip integration is the key to achieving intelligent sensors, in particular monolithic integrated MEMS sensor technology is todays system-on-chip can achieve one of the key technologies. Clearly, monolithic integration of the various technical difficulties analysis of MEMS and have already given the various monolithic integration of MEMS technology is essential.1. Monolithic integration of MEMS technology advantages and the challenges facing。MEMS and CMOS achieve working together, the separate manufacturing CMOS MEMS sensors and integrated circuits, and then cut from their chips, fixed in a common substrate, and, bonded connection, thereby bringing the two integration, This is the so-called mixed (hybrid) method. This method does not produce MEMS manufacturing process for CMOS circuits pollution At the same time, both the production process Noninterference. However, due to signal bonding point and fuses, resulting in high-frequency applications, decline in the quality of signal transmission, and to develop two production lines to increase the cost of the product. In order to address some performance issues, and lower manufacturing costs, and proposed to do in the part of MEMS and CMOS circuits with a substrate, which is produced compatible with CMOS technology or monolithic integrated MEMS technology called CMOS-MEMS technology. This method relative hybrid method generally have the following advantages: First, the performance can be greatly improved, because parasitic capacitance and crosstalk phenomenon can be significantly reduced; second, hybrid method requires sophisticated technology to reduce packaging Sensor Interface affected, and monolithic integration requires packaging technology is relatively simple and 外文翻譯資料2therefore, lower cost sensors; third, monolithic integrated sensor array sensor technology is the need to overcome the array sensor and external decoding circuit an effective interconnect bottleneck; Fourth, the development of monolithic integrated mixed development of MEMS products than MEMS products for a short time, and to develop low cost.Monolithic integration of MEMS technology under some of MEMS devices and CMOS circuit can be divided into different order processing before CMOS (pre-CMOS), mixed CMOS (intermediate-CMOS), and after the CMOS (post-CMOS) integrated approach.Post-CMOS approach is in the processing of silicon CMOS circuits End, through some additional MEMS micro-processing technology to achieve monolithic integrated MEMS system, at present, monolithic integration of MEMS technology in this way mainly based. Post-CMOS approach is the main issue on MEMS processing temperature CMOS circuit performance in front of an impact on more serious is that the technology behind high-temperature MEMS processing temperature and metal CMOS process ahead of incompatibility. In the present study as the most polysilicon layer structure of the MEMS example, the densification of phosphorus glass annealing temperature is 950 due to a structural polysilicon layer of stress annealing temperature reached 1050 , which will enable CMOS devices junction depth migration occurred. In particular 800 shallow junction devices junction depth migration will affect device performance. On the other hand, the conventional aluminum metallization process, when the temperature reaches 400-450 , the reliability of CMOS circuits will be severely affected. From the above we can see that: how to overcome behind high-temperature MEMS processing temperature on the micro-structure of the front end processing has been the impact of CMOS circuits integrated MEMS single-chip solution is key to the system. At present, the international community is essential to resolve this issue through three ways: First is the interconnection of refractory metals instead of aluminum metal interconnect, for example, the University of Berkeley to replace tungsten aluminum metal interconnect programmes, such follow-up increased tolerance MEMS processing for high temperature; The second is produced by finding low temperature mechanical properties and excellent substitute materials as structural polysilicon layer; third way is to use its existing structure CMOS MEMS layer as a layer structure.Pre-CMOS integrated approach is to create structure MEMS manufacturing CMOS circuits, although this integrated CMOS technology to overcome post-CMOS method of high-temperature MEMS Technology on CMOS circuits affected, but because of the existence of micro-vertical structure, and therefore, there sensor and circuit interconnection level coverage, but also in the 外文翻譯資料3process of CMOS circuits on the micro-structure protection is also a need to consider the issue. Even fine-tune the optimization of CMOS process, such as: gate oxide may be heavily doped layer impact of the structure. In addition, the MEMS technology can not process any of the metal or other materials, such as piezoelectric polymers, and so on, makes this method only suitable for some special applications.Intermediate-CMOS circuits in the CMOS production process to insert some MEMS micro-processing technology to achieve monolithic integrated MEMS approach. This approach has been very mature and have a lot of commercialization of products, is the first study of a single-chip integration method is to solve the pre - and post-CMOS CMOS method effective method problems, but due to the need for the existing standard CMOS or larger BiCMOS process changes, therefore, the use of this method is limited.2.The main monolithic integrated MEMS technology statusAt present, the monolithic integration of MEMS technology mainly to post-CMOS technologies, through a series of compatible with CMOS process on the surface micro-machining and processing to achieve monolithic integration of MEMS. Can be divided into two kinds: one is in the top layer CMOS structure to a structure layer deposition micro-machining; the other is directly CMOS layer structure as the original structure of the MEMS micro-machined.2.1 Deposition of new structural materials for the structure of integrated MEMS technology2.1.1 Polysilicon layer structure as the surface micro-machining technology integrationThis process is typical of modules developed at the University of Berkeley Integrated CMOS and MEMS Technology (modular integration of CMOS with micro-structures, MICS), this method is for the micro-structural polysilicon layer, phosphorus silicon glass (PSG) as a sacrificial layer The surface micro-machining technology. A refractory metal tungsten metal interconnect instead of aluminum metal interconnect to bear behind the polysilicon production needs of micro-structure of high-temperature, but at 600 , tungsten and silicon form easily response by the University of Berkeley in the Contacts release a TiN barrier layer to address this problem. MICS process is the basic process: the completion of tungsten metal CMOS process, the deposition of 300 10-10nm low-temperature oxide (LTO), and then, low pressure chemical vapor deposition 200 10-10nm protection of the silicon nitride film has been produced CMOS circuits, micro-structure and corrosion End CMOS circuit contact hole, No. 1 layer deposition scene doped polysilicon (350 10-10), as CMOS circuits and micro-structure of interconnection lines, in the above deposition to a um PSG thick as a sacrificial layer thickness and deposition of 2 um polysilicon layer structure. No. 外文翻譯資料42 through another layer polysilicon deposition of a layer of 0.5 um PSG, as well as nitrogen environment in the 1000 rapid thermal annealing for 1 min as a structure to reduce stress polysilicon layer. Finally, the structure of graphics and polysilicon etching out its corrosion layer below the sacrifices (PSG) for the release of micro-structure.2.1.2 Other materials for the structure of the surface micro-machining technology integrationPolycrystalline silicon germanium polysilicon not only with the excellent mechanical properties similar, and, low temperature deposition compatible with the CMOS process, therefore, is being extensively studied. Developed at the University of Berkeley-based structural layer of silicon germanium technology and MICS technology similar. Major technological innovations: First, the protective layer using different materials, before 835 MICS process is the LPCVD silicon nitride, and now it is using a two-tier LTO and intermediate folder is not a stereotypical silicon (a-Si) as a CMOS circuit protective layer, in which the two-step deposition of a-Si, the first step in the deposition 450 ; step deposition in the 410 , this will not damage the temperature of aluminum metal CMOS circuit; Second, the low amylin plot structure as a temperature polysilicon layer of germanium materials, the low pressure chemical vapor deposition (LPCVD) temperature only 400 using rapid thermal annealing temperature of only 5.5 for 30 s. MICS and the temperature polysilicon deposition of more than 600 . From the above two points, we can see that the whole follow-up MEMS processing temperature does not exceed 450 , therefore, not of aluminum metal interconnect CMOS circuits have greatly affected.Aluminum used as a structural material will be a great success, the most successful is the Texas Instruments developed cryogenic surface micro-machining technology, and use this technology successfully produced digital micromirror device (DMD). Technical innovation in the use of sputtering performance as aluminum structural material, and using photoresist as a sacrificial layer, which makes low-temperature post-processing production has been below the SRAM cells were not damaged.Lead zirconate titanate (PZT) of the material has an excellent result piezoelectric properties, pyroelectric properties of ferroelectric properties and dielectric properties and is widely used in ferroelectric memory, as well as high-dielectric materials. At the same time, we can also use lead zirconate titanate piezoelectric effect produced micro-sensors and micro-actuators. PZT thin film silicon technology and integration technology compatible, such as the present based on the metal-organic chemical vapor deposition (OCVD) Methods PZT thin films temperature has been reduced 外文翻譯資料5to 430 to 75 , the temperature is lower, therefore, use of such materials as structural layer is a very hopeful and CMOS process integration.2.2 CMOS structure to the original layer to the structure of integrated MEMS technology2.2.1 Sacrifice aluminum micro-machining technologyIf CMOS metal compounds used for the expense of materials, there may be fully compatible with CMOS technology and surface micro-machining small art, this method is called sacrifice aluminum etching (sacrificial aluminum etching, SALE). In many CMOS process, use two layers of aluminum alloy by a metal layer. No. 1 as a sacrificial layer of metal was removed, can create metal dielectric compounds; Layer 2 and passivation of the metal component, 2-layer metal between two dielectric between appropriate structure, they could serve as a mirror electrodes, heat or electric resistance regulator. The basic process include: (1) the protection of electrical contacts are not connected etching (2) corrosion sacrifice aluminum layer; (3) removal rinsed Boundary structure inside the etching agent; (4)-drying bodies.2.2.2 Monocrystal silicon etching and metal activation method.Monomer silicon etching and metal activation method (single crystal reactiveetching and metallization, SCREAM) can be used for manufacturing, beam, the bridge structure, and even silicon can be used to create more complex structures. This approach starts at the End manufacture silicon CMOS circuits, first of all, a layer of coverage deposition contact hole silicon oxide, oxide layer to protect it from the back of CMOS circuits affected, and through reactive ion etching (RIE) of this graphics Oxide layer shielding layer; then RIE etching silicon trench, the depth of up to 10 um, silicon oxide thin film deposition down, and the level of coverage in the side surface. By reactive ion etching of the oxide surface level off due to a vertical surface to be protected, the second reactive ion etching silicon; Finally, the isotropic etch silicon, the release of the microstructure of a suspension, at the same time, etching contact hole oxides, and Sputtering metal, this layer of metal deposition to the aspect ratio of the beam into a capacitive elements with thick resist masking agent for the graphics mode of metal layers. As each step of SCREAM are below 300 under the temperature and, therefore, is compatible with CMOS circuits.2.2.3 Large aspect ratio of CMOS-MEMS TechnologyGamegle Melloa University and the development of CMOS-compatible dry etching method, which isotropic silicon etch applications have insulation film, CMOS dielectric and metal layers in this process, not only for the metal interconnect, but also as a micro-mechanical structure tail. Basic process: First, the standard CMOS process using three-metal process to achieve 0.5 upmN Well, 外文翻譯資料6secondly, metal layers 1 and 2 were used as electrical activity layer, and layer 3 as a micro-machining etching mask. Application of the compound CHF3/O2 reactive ion etching (RIE), the entire chip passivation layer to be removed, in the three-tier regional disconnect metal, CMOS laminated film has been etched to the basement, and above covered with Layer 3 CMOS metal thin film laminated retained intact; Finally, the use of SP6/O2 plasma etching in the micro-structural wall not under isotropic etch silicon substrate. Narrow insulating layer and conductive layer fused to create beams and bridges, such as: Comb drive the micro-structure.2.2.4 Processing CMOS-MEMS TechnologyMainly through the etching of silicon substrates, such as processing technology to form the necessary MEMS structure, the technology mainly to the University of Zurich-based. Can be viewed in a positive etching silicon substrate, but also from negative etching silicon substrate, using anisotropic etching (100) in the direction of the characteristics of the silicon etching could be positive not closed micro-structure, such as beams and support film , the choice of etching can be tetramethyl ammonium hydroxide solution (TMATH) or ethylene diamine solution (EDP). From what has been done through the back of the silicon wafer of silicon can be pitting the closure of the dielectric film, the need for a definition of additional patch mask the size of the commonly used candle is engraved on KOH. XeF2 dry etching using the post-CMOS technology has also made great development. XeP2 is an anisotropic etching of silicon, etching at high velocity, it is an inert gas xenon rare compounds. XeP2 neither IC insulating layer etching, etching aluminum or metal compounds, therefore, and CMOS compatible. After the appropriate regional design, connectivity and processing mask, opened in designated parts insulating layer, so that local exposure to silicon substrate etching agent. XeF2 because that is not etched ceramic, not plastic etching and thus suitable for CMOS integrated micro-processing system. In the use of this method can be completed with CMOS chip micro-etching mask institutions.3.Development Trend Monolithically integrated MEMS technology has been developing for more than 10 years, has been the rapid development has also seen the emergence of a MEMS manufacturing services organizations and enterprises, which will be some special organizations or directly from the IC manufacturers to provide MEMS processing. IC Microsystems representative of the direction of technology development organizations, including the United States and Europe TIMACMP MOSIS.Europractice; North Kaluona state Croons Integrated Microsystems Inc., in addition to 外文翻譯資料7providing the basic CMOS process, the body also provides micro-machining and surface emblem processing, LIGA process, as well as multi-user MEMS technology; the United States Sandia National Laboratory development of the multi-storey hyperplane polysilicon technology has been commercialized in Europe in the application-specific integrated circuit manufacturing technology research, including Austria Microsystems and Switzerlands EM Microelectronics. There are many special silicon-based sensor technology has also been finding out, for example, Germanys Luobaitebo Oxfam and the Norwegian SensoNor companies. Judging from the current situation, integrated MEMS technology will have the following trends: (1) post-CMOS integrated approach will continue to be the main future development of technology, and the existing laboratories have developed various post-CMOS single-chip integrated MEMS technology industry; (2) in the integrated MEMS system more complex integrated circuit including digital interfaces and microcontrollers, so that a more powerful, cheaper intelligent systems; (3) the development of CMOS chip packaging technology protection against environmental impacts, not only need to develop a system to integrate the MEMS package, but also need to adapt to the development of the single-chip package integrated MEMS technology.4.Concluding remarks Monolithic Integrated Intelligent MEMS sensor is the key to the development of IC industry is an important direction. Although various methods are some problems still exist, however, with its constant research and CMOS process compatibility problems will be all the solutions. In this paper, monolithic integration of MEMS technology to the requirements were discussed, and monolithic integration of various characteristics of MEMS technology, a process, at the same time, also gives future monolithic integration of MEMS technology development trend of the future.
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