USB接口信號(hào)發(fā)生器

USB接口信號(hào)發(fā)生器,usb,接口,信號(hào)發(fā)生器 生畢業(yè)設(shè)計(jì)（論文）中期報(bào)告系別班級(jí)學(xué)生姓名指導(dǎo)教師課題名稱(chēng)：USB接口波形發(fā)生器簡(jiǎn)述開(kāi)題以來(lái)所做的具體工作、取得的進(jìn)展及下一步主要工作：所做的工作：1. 在圖書(shū)館和網(wǎng)絡(luò)上查找相關(guān)資料，了解USB的原理和工程開(kāi)發(fā)的過(guò)程，為深入研究做好準(zhǔn)備。2. 查找各器件的管腳圖及其原理，列元件清單，購(gòu)買(mǎi)器件。3. 根據(jù)之前的準(zhǔn)備進(jìn)行電路的焊接工作，從元器件的特性，電路的外觀上合理的布局，完成硬件電路焊接。 4.對(duì)電路進(jìn)行調(diào)試。 取得的進(jìn)展：各模塊電路已基本實(shí)現(xiàn)，獲得的指標(biāo)和設(shè)想差距不大。下一步的主要工作：1. 解決調(diào)試中出現(xiàn)的問(wèn)題，并且分析其原因。2. 記錄調(diào)試數(shù)據(jù)，整理資料，準(zhǔn)備寫(xiě)論文。3. 總結(jié)之前所作的工作，為畢業(yè)答辯做好充分的準(zhǔn)備。 學(xué)生簽字： 年 月 日指導(dǎo)教師的建議與要求： 設(shè)計(jì)思路清晰，進(jìn)度安排合理，同時(shí)希望在以后的制作過(guò)程中要抓緊時(shí)間完成后期的工作。 指導(dǎo)教師簽字： 年 月 日天津工程師范學(xué)院畢業(yè)設(shè)計(jì)（論文）任務(wù)書(shū)題 目(包括副標(biāo)題)USB接口波形發(fā)生器教師姓名職 稱(chēng)系 別學(xué)生姓名學(xué) 號(hào)班 級(jí)成果形式A論文 B設(shè)計(jì)說(shuō)明書(shū) C實(shí)物 D軟件 E作品 任務(wù)下達(dá)時(shí)間08.11.131畢業(yè)設(shè)計(jì)（論文）課題任務(wù)的內(nèi)容和要求：（包括原始數(shù)據(jù)、技術(shù)要求、工作要求以及圖紙、程序、實(shí)物等要求）1、 畢業(yè)設(shè)計(jì)主要內(nèi)容（1）了解USB原理與工程開(kāi)發(fā)的流程。（2）深入研究并掌握電路基本功能及相關(guān)程序。（3）編程實(shí)現(xiàn)其各種功能。2、技術(shù)指標(biāo)（1）、頻率范圍是0.5Hz15999.5Hz,步進(jìn)值為0.5Hz。（2）、幅度峰峰值范圍是0V+5V,步進(jìn)值為20mV。（3）、可讀取該USB設(shè)備的各種描述符和USB總線(xiàn)的當(dāng)前幀號(hào)。3、技術(shù)要求（1）方案設(shè)計(jì)明確，程序運(yùn)行穩(wěn)定。 （2）論文寫(xiě)作規(guī)范，用詞恰當(dāng)，內(nèi)容充實(shí)（10000字以上）；（3）提交的全部材料必須符合學(xué)院下達(dá)的文件格式；2畢業(yè)設(shè)計(jì)（論文）工作進(jìn)度計(jì)劃：周 次工作內(nèi)容早進(jìn)入階段第一周第二三周第四五周第六七周第八九周第十十二周下達(dá)畢業(yè)設(shè)計(jì)任務(wù)書(shū)，收集資料，初步確定USB控制芯片的型號(hào)并了解它的工作原理初步了解USB工程開(kāi)發(fā)的原理和系統(tǒng)構(gòu)成，進(jìn)一步學(xué)習(xí)確定硬件電路設(shè)計(jì)方案，購(gòu)買(mǎi)元器件并完成硬件電路的制作 進(jìn)行軟件編程和調(diào)試。 對(duì)電路的軟件及硬件進(jìn)行整體調(diào)試。翻譯相關(guān)英文資料，完成論文初稿交老師批閱此次畢業(yè)設(shè)計(jì)將于明年二月底正式開(kāi)始，預(yù)計(jì)為期十二周完成修改并完成論文，撰寫(xiě)答辯提綱，準(zhǔn)備答辯。教研室（學(xué)科組）主任簽字： 畢 業(yè) 設(shè) 計(jì) 開(kāi) 題 報(bào) 告 USB接口波形發(fā)生器 系 別： 班 級(jí)： 1 學(xué)生姓名： 指導(dǎo)教師： 2008年 12 月 13日開(kāi)題報(bào)告填寫(xiě)要求1開(kāi)題報(bào)告作為畢業(yè)設(shè)計(jì)答辯委員會(huì)對(duì)學(xué)生答辯資格審查的依據(jù)材料之一，應(yīng)在指導(dǎo)教師指導(dǎo)下，由學(xué)生在畢業(yè)設(shè)計(jì)工作前期完成，經(jīng)指導(dǎo)教師簽署意見(jiàn)、專(zhuān)家組及系主任審查后生效；2開(kāi)題報(bào)告必須用黑墨水筆工整書(shū)寫(xiě)或按教務(wù)處統(tǒng)一設(shè)計(jì)的電子文檔標(biāo)準(zhǔn)格式（可從教務(wù)處網(wǎng)頁(yè)上下載）打印，禁止打印在其它紙上后剪貼；3畢業(yè)設(shè)計(jì)的開(kāi)題報(bào)告應(yīng)包括以下內(nèi)容：（1）主要技術(shù)指標(biāo)；（2）工作思路；（3）課題的準(zhǔn)備情況及進(jìn)度計(jì)劃；（4）參考文獻(xiàn)。4開(kāi)題報(bào)告的撰寫(xiě)應(yīng)符合科技文獻(xiàn)規(guī)范，且不少于2000字；參考文獻(xiàn)應(yīng)不少于15篇，包括中外文科技期刊、教科書(shū)、專(zhuān)著等。 5開(kāi)題報(bào)告正文字體采用宋體小四號(hào)，1.5倍行距。附頁(yè)為A4紙型，左邊距3cm，右邊距2cm，上下邊距為2.5cm，字體采用宋體小四號(hào)，1.5倍行距。6“課題性質(zhì)”一欄： 理工類(lèi)：A.理論研究 B.應(yīng)用研究 C工程設(shè)計(jì) D.軟件開(kāi)發(fā) E.其它 經(jīng)管文教類(lèi)：A.理論研究 B.應(yīng)用研究 C.實(shí)證研究 D.藝術(shù)創(chuàng)作 E.其它 “課題來(lái)源”一欄：A.科研立項(xiàng) B.社會(huì)生產(chǎn)實(shí)踐 C.教師自擬 D.學(xué)生自選“成果形式”一欄：A.論文 B.設(shè)計(jì)說(shuō)明書(shū) C.實(shí)物 D.軟件 E.作品畢業(yè)設(shè)計(jì)開(kāi)題報(bào)告課題題目課題性質(zhì)A B C D E 課題來(lái)源A B C D 成果形式A B C D E 同組同學(xué)無(wú)開(kāi)題報(bào)告內(nèi)容（可另附頁(yè)）指導(dǎo)教師意見(jiàn)（課題難度是否適中、工作量是否飽滿(mǎn)、進(jìn)度安排是否合理、工作條件是否具備等）課題難度適中、工作量飽滿(mǎn)、進(jìn)度安排合理、工作條件具備指導(dǎo)教師簽名： 月 日 專(zhuān)家組及系里意見(jiàn)（選題是否適宜、各項(xiàng)內(nèi)容是否達(dá)到畢業(yè)設(shè)計(jì)（論文）大綱要求、整改意見(jiàn)等）專(zhuān)家組成員簽字： 教學(xué)主任（簽章）： 月 日開(kāi)題報(bào)告附頁(yè)：USB接口波形發(fā)生器一、 主要技術(shù)指標(biāo)：USB是一種應(yīng)用在計(jì)算機(jī)領(lǐng)域的新型接口技術(shù)，最早由Compaq、Intel、Microsoft等多家公司于1994年11月共同提出的，其目的是使用USB來(lái)取代PC機(jī)現(xiàn)有的各種外圍接口，使外設(shè)的連接具有單一化、即插即用、熱插拔等特點(diǎn)。它的出現(xiàn)大大簡(jiǎn)化了PC機(jī)和外設(shè)的連接過(guò)程，使PC機(jī)接口的擴(kuò)展變得更加容易。可以說(shuō)，USB是計(jì)算機(jī)外設(shè)連接技術(shù)的重大變革?；谶@一思想，做了這個(gè)USB接口波形發(fā)生器，它采用直接數(shù)字頻率合成（DDFS）技術(shù)，實(shí)時(shí)將USB接收到的數(shù)據(jù)轉(zhuǎn)換成各種頻率的波形輸出，所使用的USB傳輸方式為全速同步傳輸?？梢暂敵?種波形：正鋸齒波、反鋸齒波、三角波、方波和正弦波。它實(shí)現(xiàn)的主要功能是：(1)、采用USB總線(xiàn)或外部+5V電源供電，并具有供電指示燈。(2)、采用TLC7524完成波形數(shù)據(jù)的DA轉(zhuǎn)換，并具有DA轉(zhuǎn)換指示燈。(3)、采用DAC0832完成波形幅度峰峰值的調(diào)節(jié)，范圍是0V+5V,步進(jìn)值為20mV.(4)、采用DDFS技術(shù)完成波形頻率調(diào)節(jié)，范圍是0.5Hz15999.5Hz,步進(jìn)值為0.5Hz。(5)、采用全速同步端點(diǎn)8、9、10米傳輸系統(tǒng)控制命令和波形數(shù)據(jù)。(6)、可讀取該USB設(shè)備的各種描述符和USB總線(xiàn)的當(dāng)前幀號(hào)。二、工作思路：1、系統(tǒng)的組成 本系統(tǒng)硬件電路可分為三大部分：以AN2131QC為核心的USB接口控制單元、以可編程邏輯器件EPM7064為核心的DDFS控制單元、以數(shù)模轉(zhuǎn)換器TLC7524和DAC0832為核心的波形輸出單元。系統(tǒng)框圖如下：?jiǎn)纹瑱C(jī)USB接口可編程邏輯器件列隊(duì)緩沖器D/A轉(zhuǎn)換運(yùn)算放大示波器PC機(jī)2、系統(tǒng)硬件設(shè)計(jì)：USB接口單元USB接口單元的主要實(shí)現(xiàn)芯片為Cypress公司的AN2131QC，負(fù)責(zé)完成硬件系統(tǒng)和PC機(jī)之間的數(shù)據(jù)傳輸。DDFS控制單元DDFS控制單元的主要實(shí)現(xiàn)芯片為Altera公司的EPM7064，負(fù)責(zé)控制系統(tǒng)輸出波形的頻率。波形輸出單元 波形輸出單元的主要實(shí)現(xiàn)芯片為T(mén)I公司的TLC7524和美國(guó)國(guó)家半導(dǎo)體公司的DAC0832，負(fù)責(zé)對(duì)波形數(shù)據(jù)進(jìn)行D/A轉(zhuǎn)換。課題的準(zhǔn)備情況及進(jìn)度計(jì)劃1.查找和翻閱了一定數(shù)量的參考文獻(xiàn)和相關(guān)資料并學(xué)習(xí)了USB2.0原理與工程開(kāi)發(fā)。基本確定了畢業(yè)設(shè)計(jì)的主要研究路線(xiàn)以及應(yīng)該著重解決的關(guān)鍵問(wèn)題。主要研究路線(xiàn)：本課題從系統(tǒng)要求分析入手，將整個(gè)系統(tǒng)分成三個(gè)部分，分析和討論了各個(gè)部分的電路原理和實(shí)現(xiàn)方法。詳細(xì)討論了系統(tǒng)的各種工作情況，并得到了系統(tǒng)各個(gè)部分的主要構(gòu)成。根據(jù)對(duì)畢業(yè)設(shè)計(jì)工作的了解，擬定了初步的進(jìn)度計(jì)劃。序號(hào)畢業(yè)設(shè)計(jì)階段性工作及成果時(shí)間安排1初步了解USB工程開(kāi)發(fā)的原理和系統(tǒng)構(gòu)成，進(jìn)一步學(xué)習(xí)2008.122009.12確定硬件電路設(shè)計(jì)方案，購(gòu)買(mǎi)元器件并完成硬件電路的制作與調(diào)試2009.12009.23進(jìn)行軟件編程和調(diào)試2009. 22009.34對(duì)電路的軟件及硬件進(jìn)行整體調(diào)試2009. 32009.45翻譯相關(guān)英文資料，完成論文初稿交老師2009. 42009.56修改并完成論文，撰寫(xiě)答辯提綱，準(zhǔn)備答辯2009. 52009.6 三、參考文獻(xiàn)1 尹勇，王洪成編著 單片機(jī)開(kāi)發(fā)環(huán)境Vision 2使用指南 2004 2 李英偉 編著 USB 2.0原理與工程開(kāi)發(fā) 20073 武安河 編著 Windows 2000/XP WDM設(shè)備驅(qū)動(dòng)程序開(kāi)發(fā) 20054 周立功 編著 USB 2.0與OTG規(guī)范及開(kāi)發(fā)指南 20045 蕭世文 編著 USB 2.0硬件設(shè)計(jì) 2002 6 廖濟(jì)林 編著 USB 2.0應(yīng)用系統(tǒng)開(kāi)發(fā)實(shí)例精講 20067 薛園園 編著 USB應(yīng)用開(kāi)發(fā)技術(shù)大全 2007 8 許永和編著 健蓮科技改編 USB外圍設(shè)備設(shè)計(jì)與應(yīng)用 20029 張弘編著 USB接口設(shè)計(jì) 2002 10 胡曉軍，張愛(ài)成編著 USB接口開(kāi)發(fā)技術(shù) 200511 李肇慶 廖峰 劉建存編著 USB接口技術(shù) 2004 12 劉韜，樓興華編著 FPGA數(shù)字電子系統(tǒng)設(shè)計(jì)與開(kāi)發(fā)實(shí)例導(dǎo)航 2005 13 錢(qián)峰編著 EZ-USB FX2單片機(jī)原理、編程及應(yīng)用 2006 14 許永和編著 8051單片機(jī)USB接口程序設(shè)計(jì) 2004 15 劉兵 編著 微型計(jì)算機(jī)通信與接口技術(shù) 200816 厲榮衛(wèi)主編 微機(jī)原理與接口技術(shù) 2006 17 馬偉 編著 計(jì)算機(jī)USB系統(tǒng)原理及其主從機(jī)設(shè)計(jì) 200418 (美) Hyde John 著 USB設(shè)計(jì)應(yīng)用實(shí)例 2003 19 網(wǎng)絡(luò)資源：http:/www.21ic.com、http:/www.mcufans.com 畢業(yè)設(shè)計(jì)（論文）指導(dǎo)檢查工作記錄表系別班級(jí)學(xué)生姓名指導(dǎo)教師課題名稱(chēng)USB接口波形發(fā)生器時(shí)間內(nèi)容及指導(dǎo)記錄指導(dǎo)教師簽字08.11.13下達(dá)畢業(yè)設(shè)計(jì)任務(wù)書(shū)08.12.13開(kāi)題報(bào)告第一周方案論證第二周方案修改、方案確定第三周設(shè)計(jì)電路第四周設(shè)計(jì)電路第五周設(shè)計(jì)電路方案確定第六周購(gòu)買(mǎi)電子元器件第七周提交中期報(bào)告第八周制作電路、軟件編程、調(diào)試電路第九周制作電路、軟件編程、調(diào)試電路第十周撰寫(xiě)畢業(yè)設(shè)計(jì)、提交畢業(yè)設(shè)計(jì)初稿第十一周修改畢業(yè)設(shè)計(jì)、畢業(yè)論文答辯第十二周畢業(yè)論文答辯、總結(jié)、按照學(xué)院要求提交全部標(biāo)準(zhǔn)材料注：本表格同畢業(yè)設(shè)計(jì)（論文）一同裝訂成冊(cè)，由所在單位歸檔保存。摘 要本系統(tǒng)介紹USB接口波形發(fā)生器的設(shè)計(jì)。它采用直接數(shù)字頻率合成（DDFS）技術(shù)，實(shí)時(shí)將USB接收到的數(shù)據(jù)轉(zhuǎn)換成各種頻率的波形輸出，所使用的USB傳輸方式為全速同步傳輸。它可以輸出正鋸齒波、反鋸齒波、三角波、方波和正弦波5種波形。其硬件電路由以USB控制芯片AN2131QC為核心的USB接口單元、以可編程邏輯器件EPM7064為核心的DDFS單元、以數(shù)模轉(zhuǎn)換器TLC7524和DAC0832為核心的波形輸出單元三大部分構(gòu)成。其中，USB接口單元負(fù)責(zé)完成硬件系統(tǒng)和PC機(jī)之間的數(shù)據(jù)傳輸，DDFS控制單元負(fù)責(zé)控制系統(tǒng)輸出波型的頻率，波形輸出單元負(fù)責(zé)對(duì)波形數(shù)據(jù)進(jìn)行DA轉(zhuǎn)換，并負(fù)責(zé)控制輸出波形幅度峰峰值。它的系統(tǒng)軟件包括Keil C51語(yǔ)言編寫(xiě)的AN2131QC芯片固件程序、Visual C+語(yǔ)言編寫(xiě)的USB設(shè)備驅(qū)動(dòng)程序和Win32應(yīng)用程序。其波形頻率范圍是0.5Hz15999.5Hz,步進(jìn)值為0.5Hz，幅度范圍是0V+5V,步進(jìn)值為20mV。關(guān)鍵詞: USB接口；任意波形；DDFS；波形發(fā)生器；Visual C+語(yǔ)言ABSTRACTThis system introduces the design of USB interface wave form generator. It uses direct digital frequency synthesizer (DDFS) techniques, real-time will be received USB data into various frequency waveform output, used for full-speed USB transfer mode asynchronous transfer. It can output is sawtooth, anti-aliasing wave, triangle wave, square wave and sine wave . The hardware circuit to USB controller chip by AN2131QC at the core of the USB interface unit to EPM7064 programmable logic device as the core unit DDFS to DAC TLC7524 and the DAC0832 output waveform at the core constitute the majority of unit three. Which, USB interface unit is responsible for the completion of the hardware systems and PC data transfer between machines, DDFS control unit control system is responsible for the frequency of the output waveform, waveform output unit is responsible for the waveform data DA conversion, and is responsible for control of output waveform peak-to-peak amplitude. Its system software, including the Keil C51 language AN2131QC firmware chip, Visual C + + language prepared USB device drivers and Win32 applications. Its frequency adjustment range is 0.5Hz 15999.5Hz, step value of 0.5Hz and amplitude of the adjustment range of 0V +5 V, step value of 20mV. Key words: USB interface; Arbitrary Waveform; DDFS; waveform generator; Visual C+ + Language英文資料及中文翻譯PDIUSBD12-USB interface device with parallel busThe PDIUSBD12 is a cost and feature optimized USB device. It is normally used in microcontroller based systems and communicates with the system microcontroller over the high-speed general purpose parallel interface. It also supports local DMA transfer.This modular approach to implementing a USB interface allows the designer to choose the optimum system microcontroller from the available wide variety. This flexibility cuts down the development time, risks, and costs by allowing the use of the existing architecture and minimize firmware investments.This results in the fastest way to develop the most cost effective USB peripheral solution.The PDIUSBD12 fully conforms to the USB specification Rev. 2.0 (basic speed). It is also designed to be compliant with most device class specifications: Imaging Class, Mass Storage Devices, Communication Devices, Printing Devices, and Human Interface Devices.Assuch, the PDIUSBD 12 is ideally suited for many peripherals like Printer, Scanner, External Mass Storage (Zip Drive), Digital Still Camera, etc. It offers an immediate cost reduction for applications that currently use SCSI implementations.The PDIUSBD12 low suspend power consumption along with the Lazy Clock output allowsfor easy implementation of equipment that is compliant to the ACPI(TM),OnNOW(TM), and USB power management requirements. The low operating power allows the implementation of bus powered peripherals. In addition; it also incorporates features like SoftConnect(TM), GoodLink(TM), programmable clock output, low frequency crystal oscillator, and integration of termination resistors. All of these features contribute to significant cost savings in the system implementation and at the same time ease the implementation of advanced USB functionality into the peripherals.1. DMA transferDirect Memory Address (DMA) allows an efficient transfer of a block of data between thehostandlocalsharedmemory.UsingaDMAcontroller, data transfer between thePDIUSBD12s main endpoint (endpoint 2) and local shared memory can happen autonomously without local CPU intervention.Preceding any DMA transfer, the local CPU receives from the host the necessary setup information and programs the DMA controller accordingly. Typically, the DMA controller is set up for demand transfer mode and the byte count register and the address counter are programmed with the right values. In this mode, transfers occur only when the PDIUSBD12 requests them and are terminated when the byte count register reaches zero. After the DMA controller has been programmed, the DMA enable bit of the PDIUSBD12 is set by the local CPU to initiate the transfer.The PDIUSBD12 can be programmed for single-cycle DMA or burst mode DMA. In single-cycle DMA, the DMREQ pin is deactivated for every single acknowledgement by the DMACK_N before being re-asserted. In burst mode DMA, the DMREQ pin is kept active for the number of bursts programmed in the device before going inactive.This process continues until the PDIUSBD12 receives a DMA termination notice through pin EOT_N. This will generate an interrupt to notify the local CPU that DMA operation is completed.For DMA read operation,the DMREQ pin will only be activated whenever the buffer is full, signalling that the host has successfully transferred a packet to the PDIUSBD12.With the double buffering scheme, the host can start filling up the second buffer while the first buffer is being read out. This parallel processing increases the effective throughput.When the host does not fill up the buffer completely (lessthan64 bytesor 128 bytes for single direction ISO configuration), the DMREQ pin will be deactivatedat the last byte of the buffer regardless of the current DMA burst count. It will be re-asserted on the next packet with a refreshed DMA burst count.Similarly, for DMA write operations, the DMREQ pin remains active whenever the buffer is not full. When the buffer is filled up, the packet is sent over to the host on the next IN token and DMREQ will be reactivated if the transfer was successful. Also, the double buffering scheme here will improve throughput. For non-isochronous transfer (bulk and interrupt), the buffer needs to be completely filled up by the DMA writeoperation before the data is sent to the host. The only exception is at the end of DMA transfer, when the reception of pin EOT_N will stop DMA write operation and the buffer content will be sent to the host on the next IN token.For isochronous transfers, the local CPU and DMA controller have to guarantee that they are able to sink or source the maximum packet size in one USB frame (1 ms).The assertion of pin DMACK_Nautomatically selects the main endpoint (endpoint 2), regardless of the current selected endpoint. The DMA operation of the PDIUSBD12 can be interleaved with normal I/O access to other endpoints.DMA operation can be terminated by resetting the DMA enable register bit or the assertion of EOT_N together with DMACK_N and either RD_N or WR_N.The PDIUSBD12 supports DMA transfer in single address mode and it can also work in dual address mode of the DMA controller. In the single address mode, DMA transfer is done via the DREQ, DMACK_N, EOT_N, WR_N and RD_N control lines.In the dual address mode, pins DMREQ, DMACK_N and EOT_N are not used; instead CS_N, WR_N and RD_N control signals are used. The I/O mode TransferProtocol of PDIUSBD12 needs to be followed. The source of the DMAC is accessed during the read cycle and the destination during the write cycle. Transfer needs to be done in two separate bus cycles, storing the data temporarily in the DMAC.Command description2. Command procedureThere are three basic types of commands: Initialization, Data Flow and General Commands. Respectively, these are used to initialize the function; for data flow between the function and the host; and some general commands.2.1 Initialization commandsInitialization commands are used during the enumeration process of the USB network. These commands are used to enable the function endpoints. They are also used to set the USB assigned address. Set Address/EnableCode (Hex):D0Transaction: write 1 byteThis command is used to set the USB assigned address and enable the function. Set endpoint enableCode (Hex):D8Transaction: write 1 byteThegeneric/Isochronous endpoints can only been abled when the function is enabled via the Set Address/Enable command. Set modeCode (Hex):F3Transaction: write 2 bytesThe Set mode command is followed by two data writes. The first byte contains the configuration bits. The second byte is the clock division factor byte. CLOCK DIVISION The value indicates the clock division factor for CLKOUT. The FACTOR output frequency is 48 MHz/(N+1) where N is the Clock Division Factor. The reset value is 11. This will produce the output frequency of 4 MHz which can then be programmed up or down by the user. The minimum value is 1 giving the range of frequency from 4 to 24 MHz. The minimum value of N is 0, giving a maximum frequency of 48 MHz.The maximum value of N is 11 giving a minimum frequency of 4 MHz.The PDIUSBD12 design ensures no glitching during frequency change. The programmed value will not be changed by a bus reset. Set DMACode (Hex): FBTransaction: read/write 1 byteThe set DMA command is followed by one data write/read to/from the DMA configuration register.DMA Configuration register: During DMA operation, the two-byte buffer header (status and byte length information) is not transferred to/from the local CPU. This allows DMA data to be continuous and not interleaved by chunks of this headers.For DMA read operations, the header will be skipped by the PDIUSBD12. For DMA write operations, the header will be automatically added by the PDIUSBD12. This provides for a clean and simple DMA data transfer.2.2 Data flow commandsData flow commands are used to manage the data transmission between the USB endpoints and the external microcontroller. Much of the data flow is initiated via an interrupt to the microcontroller. The microcontroller utilizes these commands to access and determine whether the endpoint FIFOs have valid data. Read interrupt registerCode (Hex):F4Transaction: read 2 bytesThis command indicates the origin of an interrupt. The endpoint interrupt bits (bits 0 to 5) are cleared by reading the endpoint last transaction status register through Read Last Transaction Status command. The other bits are cleared after reading the interrupt registers. Select EndpointCode (Hex):00 to 05Transaction: read 1 byte (optional)The Select Endpoint command initializes an internal pointer to the start of the selected buffer. Optionally, this command can be followed by a data read, which returns this byte.FULL/EMPTY: A 1 indicates the buffer is full, 0 indicates an empty buffer.STALL: A 1 indicates the selected endpoint is in the stall state.Fig 11. Select Endpoint command: bit allocation. Read Endpoint statusCode (Hex):80 to 85Transaction: read 1 byte Read last transaction status registerCode (Hex):40 to 45Transaction: read 1 byteThe Read Last Transaction Status command is followed by one data read that returns the status of the last transaction of the endpoint. This command also resets the corresponding interrupt flag in the interrupt register, and clears the status, indicating that it was read.This command is useful for debugging purposes. Since it keeps track of every transaction, the status information is overwritten for each new transaction. Read bufferCode (Hex):F0Transaction: read multiple bytes (max. 130)The Read Buffer command is followed by a number of data reads, which returns the contents of the selected endpoint data buffer. After each read, the internal buffer pointer is incremented by 1.The buffer pointer is not reset to the top of the buffer by the Read Buffer command.This means that reading or writing a buffer can be interrupted by any other command (except for Select Endpoint).The data in the buffer are organized as follows:* byte 0: reserved; can have any value* byte 1: number/length of data bytes* byte 2: data byte 1* byte 3: data byte 2* etc.The first two bytes will be skipped in the DMA read operation. Thus, the first read will get Data byte 1, the second read will get Data byte 2, etc. The PDIUSBD12 can determine the last byte of this packet through the EOP termination of the USB packet. Write bufferCode (Hex):F0Transaction: write multiple bytes (max. 130)The Write Buffer command is followed by a number of data writes, which load the endpoints buffer. The data must be organized in the same way as described in the Read Buffer command. The first byte (reserved) should always be 0.During DMA writes operation, the first two bytes will be bypassed. Thus, the first write will write into Data byte 1, the second write will write into Data byte 2, etc. For non-isochronous transfer(bulk or interrupt), the buffer should be completely filled before the data is sent to the host and a switch to the next buffer occurs. The exception is at the end of DMA transfer indicated by activation of EOT_N, when the current buffer content (completely full or not) will be sent to the host.Remark: There is no protection against writing or reading over a buffers boundary or against writing into an OUT buffer or reading from an IN buffer. Any of these actions could cause an incorrect operation.Data in an OUT buffer are only meaningful after asuccessful transaction.The exception is during DMA operation on the main endpoint (endpoint 2), in which case the pointer is automatically pointed to the second buffer after reaching the boundary (double buffering scheme). Clear bufferCode (Hex):F2Transaction: noneWhen a packet is received completely, an internal endpoint buffer full flag is set. All Subsequent packets will be refused by returning a NAK.When the microcontroller has read the data, it should free the buffer by the Clear Buffer command. When the bufferis cleared, new packets will be accepted. Validate bufferCode (Hex): FATransaction: noneWhen the microprocessor has written data into an IN buffer, it should set the buffer full flag by the Validate Buffer command. This indicates that the data in the buffer are valid and can be sent to the host when the next IN token is received. Set endpoint statusCode (Hex):40 to 45Transaction: write 1 byteA stalled control endpoint is automatically unstalled when it receives a SETUP token, regardless of the content of the packet. If the endpoint should stay in its stalled state, the microcontroller can re-stall it.When a stalled endpoint is unstalled (either by the Set Endpoint Status command or by receiving a SETUP token), it is also re-initialized. This flushes the buffer and if it is an OUT buffer it waits for a DATA 0 PID, if it is an IN buffer it writes a DATA 0 PID.Even when unstalled, writing Set Endpoint Status to 0 initializes the endpoint.2.3 General commandsSend resumeCode (Hex)：F6Transaction：noneSends an upstream resume signal for 10 ms.This command is normally issued when the device is in suspend. The RESUME command is not followed by a data read or write.Read current frame numberCode (Hex)：F5Transaction：read 1 or 2 bytesThis command is followed by one or two data reads and returns the frame number of the last successfully received SOF. The frame number is returned Least Significant byte first.PDIUSBD12帶并行總線(xiàn)的USB接口器件PDIUSBD12是一款性?xún)r(jià)比很高的USB器件，它通常用作微控制器系統(tǒng)中實(shí)現(xiàn)與微控制器進(jìn)行通信的高速通用并行接口，它還支持本地的DMA傳輸。這種實(shí)現(xiàn)USB接口的標(biāo)準(zhǔn)組件使得設(shè)計(jì)者可以在各種不同類(lèi)型微控制器中選擇出最合適的微控制器。這種靈活性減小了開(kāi)發(fā)的時(shí)間，風(fēng)險(xiǎn)以及費(fèi)用（通過(guò)使用已有的結(jié)構(gòu)和減少固件上的投資），從而用最快捷的方法實(shí)現(xiàn)最經(jīng)濟(jì)的USB外設(shè)的解決方案。PDIUSBD12完全符合USB1.1版的規(guī)范，它還符合大多數(shù)器件的分類(lèi)規(guī)格，成像類(lèi)海量存儲(chǔ)器件，通信器件，打印設(shè)備以及人機(jī)接口設(shè)備。同樣地，PDIUSBD12理想地適用于許多外設(shè)。例如，打印機(jī)，掃描儀，外部的存儲(chǔ)設(shè)備（Zip驅(qū)動(dòng)器）和數(shù)碼相機(jī)等等。它使得當(dāng)前使用SCSI的系統(tǒng)可以立即降低成本。PDIUSBD12所具有的低掛起功耗連同LazyClock輸出可以滿(mǎn)足使用ACPI，OnNOW和USB電源管理的要求，低的操作功耗可以應(yīng)用于使用總線(xiàn)供電的外設(shè)。此外它還集成了許多特性，包括SoftConnetTM，GoodLinkTM，可編程時(shí)鐘輸出，低頻晶振和終止寄存器集合。所有這些特性都為系統(tǒng)顯著節(jié)約了成本，同時(shí)使USB功能在外設(shè)上的應(yīng)用變得容易。1. DMA傳輸 直接存儲(chǔ)器尋址（DMA）允許在主端點(diǎn)和本地共享存儲(chǔ)器間實(shí)現(xiàn)數(shù)據(jù)塊的有效傳輸。使用DMA控制器，PDIUSBD12的主端點(diǎn)和本地共享存儲(chǔ)器間的數(shù)據(jù)傳輸可自主進(jìn)行而不需要本地CPU的干預(yù)。要處理任何DMA傳輸，本地CPU從主機(jī)接收必要的SETUP信息并對(duì) DMA控制器進(jìn)行相應(yīng)的編程，典型的對(duì)DMA控制器的傳輸模式，字節(jié)計(jì)數(shù)寄存器和地址計(jì)數(shù)器進(jìn)行正確的編程。在該模式下，PDIUSBD12發(fā)出請(qǐng)求時(shí)開(kāi)始傳輸。當(dāng)字節(jié)計(jì)數(shù)器減少為零時(shí)終止。在DMA控制器編程之后，本地CPU在初始化傳輸時(shí)將PDIUSBD12中的DMA使能位置位。PDIUSBD12可編程為單周期DMA或突發(fā)模式DMA。在單周期DMA中，DMREQ在每單個(gè)應(yīng)答后直到被DMACK_N重新激活之前保持無(wú)效。在突發(fā)模式DMA中，DMREQ在器件中突發(fā)編程時(shí)一直保持有效。該過(guò)程持續(xù)到PDIUSBD12通過(guò)EOT_N接收到一個(gè)DMA終止信息。這時(shí)產(chǎn)生一個(gè)中斷指示本地CPU DMA操作已經(jīng)完成。在DMA讀操作時(shí)DMREQ僅當(dāng)緩沖區(qū)完全表示主機(jī)成功的發(fā)送了一個(gè)信息包到PDIUSBD12時(shí)才有效。由于具有雙緩沖配置，主機(jī)可以在第一個(gè)緩沖區(qū)被讀出時(shí)對(duì)第二個(gè)緩沖區(qū)進(jìn)行填充，這種并行的處理有效的增加了數(shù)據(jù)吞吐量。當(dāng)主機(jī)沒(méi)有完全填滿(mǎn)緩沖區(qū)的情況下（單向ISO配置時(shí)小于64或128字節(jié)），DMREQ會(huì)在緩沖區(qū)的最后一個(gè)字節(jié)時(shí)無(wú)效 而不管當(dāng)前的DMA突發(fā)計(jì)數(shù)。在更新了DMA突發(fā)計(jì)數(shù)的下一個(gè)包發(fā)送時(shí)，DMREQ再次被激活。DMA的寫(xiě)操作與之相似，當(dāng)緩沖區(qū)未裝滿(mǎn)時(shí)，DMREQ一直有效。當(dāng)緩沖區(qū)填滿(mǎn)時(shí)，在下一個(gè)IN標(biāo)志將信息包送入主機(jī)。當(dāng)傳輸完成之后，DMREQ變?yōu)闊o(wú)效。同樣的，雙緩沖配置在這也改善了數(shù)據(jù)的吞吐量。在非同步傳輸中，批量模式和中斷。在數(shù)據(jù)被發(fā)送到主機(jī)之前，緩沖區(qū)需要通過(guò)DMA寫(xiě)操作完全裝滿(mǎn)。唯一的例外是，在DMA傳輸結(jié)束時(shí)，EOT_N接收的信號(hào)將會(huì)停止DMA寫(xiě)操作并且在下一個(gè)IN標(biāo)志置位時(shí)將緩沖區(qū)的內(nèi)容傳送到主機(jī)。在同步模式中，本地CPU和DMA控制器必須保證它們?cè)谝粋€(gè)USB幀（1ms）中能夠吞吐的最大信息包的規(guī)模。DMACK_N的激活將自動(dòng)選擇主端點(diǎn)（端點(diǎn)2）而不管當(dāng)前選擇的端點(diǎn)。PDIUSBD12的DMA操作可通過(guò)普通的I/O對(duì)其它端點(diǎn)的存取實(shí)現(xiàn)交叉存取。DMA操作可通過(guò)以下方式終止：復(fù)位DMA使能寄存器位或EOT_N加上DMACK_N以及 RD_N/WR_N的激活。PDIUSBD12支持單地址模式中的DMA傳輸，也可以在DMA控制器的雙地址模式中工作。在單地址模式中DMA通過(guò)DREQ DMACK_N,EOT_N,WR_N和RD_N控制線(xiàn)實(shí)現(xiàn)傳輸。在雙地址模式中DMREQ,DMACK_N和EOT_N未用，取而代之的是CS_N,WR_N和RD_N控制信號(hào)。需要遵循PDIUSBD12的I/O模式傳輸協(xié)議。在讀周期中對(duì)DMAC信號(hào)源進(jìn)行訪(fǎng)問(wèn)，在寫(xiě)周期對(duì)目標(biāo)進(jìn)行訪(fǎng)問(wèn)，傳輸需要兩個(gè)單獨(dú)的總線(xiàn)周期來(lái)儲(chǔ)存暫存在DMAC中的數(shù)據(jù)。2. 命令描述有3種基本的類(lèi)型的命令：初始化，數(shù)據(jù)流和通用命令。2.1 初始化命令 初始化命令在USB網(wǎng)絡(luò)進(jìn)行枚舉處理時(shí)使用，這些命令用于使能端點(diǎn)的功能，還可用來(lái)設(shè)置USB配的地址。設(shè)置地址/使能命令：D0h處理：寫(xiě)1字節(jié)該命令用于設(shè)置USB分配的地址和使能功能。 地址 寫(xiě)入的值即為地址 使能 置1使能該功能 設(shè)置端點(diǎn)使能 命令：D8h 處理：寫(xiě)1字節(jié) 通過(guò)設(shè)置設(shè)置地址/使能命令后才可使能普通/同步端點(diǎn) 普通/同步 端點(diǎn) 值1表示普通/同步端點(diǎn)使能 設(shè)置模式 命令：F3h 處理：寫(xiě)2字節(jié) 設(shè)置模式命令后跟2個(gè)寫(xiě)入的數(shù)據(jù)，第一個(gè)字節(jié)包含配置字節(jié)信息，第二個(gè)字節(jié)是時(shí)鐘分頻因素字節(jié)。配置字節(jié)無(wú)LazyClock：1 表示CLKOUT不會(huì)切換到LazyClock，0表示CLKOUT在Suspend腳變高之后切換到LazyClock，LazyClock頻率是30KHz40%，編程值將不過(guò)會(huì)被總線(xiàn)復(fù)位所改變。時(shí)鐘運(yùn)行：1表示內(nèi)部時(shí)鐘和PLL即使在掛起狀態(tài)下仍然運(yùn)行，0表示只要不需要時(shí)，內(nèi)部時(shí)鐘晶振和PLL就停止運(yùn)行，為了滿(mǎn)足嚴(yán)格的掛起電流要求，該位需要設(shè)置為0，已編程的值不會(huì)被總線(xiàn)復(fù)位所改變。中斷模式：1表示報(bào)告所有的錯(cuò)誤和“NAKing”并產(chǎn)生一個(gè)中斷。0表示只有OK被報(bào)告。編程值不會(huì)被總線(xiàn)復(fù)位所改變。SoftConnect：1表示如果VBUS可用，上行數(shù)據(jù)上拉電阻就被連接，0表示不連接。已編程的值不會(huì)被總線(xiàn)復(fù)位所改變。端點(diǎn)配置：該2位設(shè)置端點(diǎn)配置如下： 模式 0 非同步模式 模式 1 同步輸出模式 模式 2 同步輸入模式 模式 3 同步輸入/輸出模式 時(shí)鐘分頻系數(shù)字節(jié)時(shí)鐘分頻系數(shù)：該值用來(lái)表示CLKOUT的時(shí)鐘分頻系數(shù)，用N表示分頻系數(shù)，那么輸出頻率就為48MHz/(N+1)，復(fù)位值為11。這產(chǎn)生4MHz的輸出頻率，然后可由用戶(hù)自行調(diào)節(jié)。當(dāng)N為0時(shí)，得到最大頻率48MHz，當(dāng)N取最大11時(shí)，得到最小頻率4MHz。PDIUSBD12的設(shè)計(jì)確保了在改變頻率時(shí)不會(huì)出現(xiàn)干擾，已編程的值不會(huì)被總線(xiàn)復(fù)位所改變。SET_TO_ONE：該位需要在任何DMA讀或?qū)懖僮髦爸脼?。該位在上電復(fù)位值為0。復(fù)位后可將其一直設(shè)為1。僅有SOF中斷模式：將該位置1后，僅當(dāng)幀時(shí)鐘的起始（SOF）時(shí)刻引起中斷的產(chǎn)生 而不管引腳中斷模式的設(shè)置狀態(tài)設(shè)置（DMA位5）設(shè)置 DMA 命令：FBh 處理：讀/寫(xiě)1字節(jié)設(shè)置DMA命令后跟1個(gè)字節(jié)數(shù)據(jù)寫(xiě)入/讀出 DMA配置寄存器 DMA配置寄存器 在DMA操作中，兩字節(jié)的緩沖區(qū)頭（狀態(tài)和字節(jié)長(zhǎng)度信息）不參與傳送。這就允許了DMA數(shù)據(jù)的連續(xù)性，不插入信息頭。DMA讀操作時(shí)，信息頭被PDIUSBD12跳過(guò)，在DMA寫(xiě)操作時(shí)，信息頭由PDIUSBD12自動(dòng)添加，這就提供了一個(gè)簡(jiǎn)潔的DMA數(shù)據(jù)傳輸。DMA突發(fā)串：選擇DMA操作的突發(fā)串長(zhǎng)度 00 單周期 DMA 01 突發(fā)串 4 周期 DMA 10 突發(fā)串 8 周期 DMA 11 突發(fā)串 16 周期 DMA DMA使能：向該位寫(xiě)入1會(huì)通過(guò)激活DMREQ啟動(dòng)DMA操作，在激活DMREQ之前需要裝滿(mǎn)（DMA讀操作）或清空（DMA寫(xiě)操作）主端點(diǎn)緩沖區(qū)。在單周期DMA模式中，DMREQ在突發(fā)串?dāng)?shù)目耗盡后無(wú)效，然后下一個(gè)突發(fā)串時(shí)重新激活，這個(gè)過(guò)程一直持續(xù)到EOT_N和DMACK_N以及RD_N或WR_N一起被激活。此時(shí)將該位置0并終止DMA操作，DMA操作也可通過(guò)直接向該位寫(xiě)入0來(lái)終止。DMA方向：該位決定了DMA傳輸時(shí)數(shù)據(jù)流的方向，1表示從外部共享存儲(chǔ)器到PDIUSBD12（DMA寫(xiě)操作），0表示從PDIUSBD12到外部共享存儲(chǔ)器（DMA讀操作）。自動(dòng)重裝：當(dāng)該位設(shè)為1，DMA操作會(huì)自動(dòng)重新啟動(dòng)。中斷腳模式：0表示正常的中斷腳模式，中斷寄存器所有位的邏輯或產(chǎn)生中斷，當(dāng)該位寫(xiě)入1時(shí)表示中斷會(huì)在USB總線(xiàn)上行數(shù)據(jù)流出現(xiàn)幀時(shí)鐘（SOF）起始位時(shí)產(chǎn)生中斷。其它中斷仍然有效。端點(diǎn)索引4中斷使能：該位為1表示只要端點(diǎn)緩沖區(qū)包含一個(gè)有效的信息包就會(huì)產(chǎn)生中斷，通常在DMA操作時(shí)關(guān)閉以減少不必要的CPU響應(yīng)。端點(diǎn)索引5中斷使能：該位為1表示只要端點(diǎn)緩沖區(qū)有效，見(jiàn)緩沖區(qū)生效命令，就會(huì)產(chǎn)生中斷，通常在DMA操作時(shí)關(guān)閉以減少不必要的CPU響應(yīng)。 2.2 數(shù)據(jù)流命令 數(shù)據(jù)流命令用于管理USB端點(diǎn)和外部微控制器之間的數(shù)據(jù)傳輸，通過(guò)微控制器中斷初始化大量的數(shù)據(jù)流。微控制器利用這些命令訪(fǎng)問(wèn)和決定端點(diǎn)的FIFO是否含有有效的數(shù)據(jù)。讀中斷寄存器 命令：F4h 處理：讀2字節(jié) 中斷寄存器字節(jié)1中斷寄存器字節(jié) 2 該命令指示中斷的來(lái)源，通過(guò)讀端點(diǎn)最后處理狀態(tài)寄存器將端點(diǎn)中斷位（位05）清零，其它位在讀中斷寄存器后被清零。總線(xiàn)復(fù)位：在總線(xiàn)復(fù)位后將產(chǎn)生一個(gè)中斷將該位置1?？偩€(xiàn)復(fù)位與通過(guò)RESET_N腳的硬件復(fù)位基本相同，有一點(diǎn)除外，就是總線(xiàn)復(fù)位產(chǎn)生一個(gè)中斷并且器件在默認(rèn)地址0處使能。掛起改變：當(dāng)PDIUSBD12沒(méi)有收到3個(gè)SOF時(shí)，將會(huì)進(jìn)入掛起狀態(tài)并將掛起改變位置位。任何掛起或喚醒狀態(tài)的改變都會(huì)將該位置位并產(chǎn)生中斷。DMA EOT：該位表示DMA操作已結(jié)束。 選擇端點(diǎn) 命令：00-05h 處理：可選讀1字節(jié) 選擇端點(diǎn)命令將內(nèi)部指針初始化到選擇的緩沖區(qū)起始位置?？蛇x的該命令可跟一個(gè)返回的讀出字節(jié)。滿(mǎn)/空 1表示緩沖區(qū)已滿(mǎn)，0 表示緩沖區(qū)為空。停止 1表示選擇的端點(diǎn)處于停止?fàn)顟B(tài)。 讀端點(diǎn)狀態(tài) 命令：80-85h 處理：讀1字節(jié) 讀最后處理狀態(tài)寄存器 命令：40-45h 處理：讀1字節(jié) 讀最后處理狀態(tài)寄存器命令后跟一個(gè)數(shù)據(jù)返回端點(diǎn)最后處理的狀態(tài)，該命令同時(shí)復(fù)位中斷寄存器中的相應(yīng)位并將狀態(tài)清零表示已經(jīng)讀取，由于它保留了每次處理的記錄，所以該命令在以調(diào)試為目的時(shí)很有用。在每次新的處理之后會(huì)將原來(lái)的狀態(tài)信息覆蓋。數(shù)據(jù)接收/發(fā)送成功：1表示數(shù)據(jù)已經(jīng)成功地接收或發(fā)送。SETUP信息包：1表示最后成功接收的信息包有一個(gè)SETUP標(biāo)志，對(duì)IN緩沖區(qū)進(jìn)行讀總為0。數(shù)據(jù)0/1包：1表示最后成功接收/發(fā)送包含有一個(gè)DATA1 PID。前一狀態(tài)未讀：1表示在前一狀態(tài)被讀出之前發(fā)生了第二個(gè)事件。讀緩沖區(qū) 命令：F0h 處理：讀多個(gè)字節(jié)，最大130 讀緩沖區(qū)命令后，返回一系列從選擇的端點(diǎn)數(shù)據(jù)緩沖區(qū)讀出的數(shù)據(jù)，每讀一個(gè)字節(jié)，內(nèi)部緩沖區(qū)指針自動(dòng)加一，讀緩沖區(qū)命令不會(huì)將緩沖區(qū)指針復(fù)位到緩沖區(qū)起始端，這意味著可被其它的命令所中斷（選擇端點(diǎn)命令除外）。緩沖區(qū)數(shù)據(jù)結(jié)構(gòu)如下 字節(jié)1：保留;可為任意值 字節(jié)2：數(shù)據(jù)字節(jié)的數(shù)目/長(zhǎng)度 字節(jié)3：數(shù)據(jù)字節(jié)1 字節(jié)4：數(shù)據(jù)字節(jié)2 頭兩個(gè)字節(jié)在DMA讀操作中可跳過(guò)。因此第一個(gè)讀出的字節(jié)是數(shù)據(jù)字節(jié)1。第二個(gè)讀出的是數(shù)據(jù)字節(jié)2等等。PDIUSBD12可通過(guò)USB信息包的EOP終止來(lái)決定包的最后一個(gè)字節(jié)。寫(xiě)緩沖區(qū) 命令：F0h 處理：寫(xiě)多個(gè)字節(jié)，最大130 寫(xiě)緩沖區(qū)命令后跟一系列需要寫(xiě)入端點(diǎn)緩沖區(qū)的數(shù)據(jù)，數(shù)據(jù)的結(jié)構(gòu)必須與前面描述的讀緩沖區(qū)命令一樣。第一個(gè)字節(jié)（保留）總為0。在DMA寫(xiě)操作中，頭兩個(gè)字節(jié)會(huì)被繞過(guò)，因此，第一個(gè)寫(xiě)入的字節(jié)是數(shù)據(jù)字節(jié)1。第二個(gè)寫(xiě)入的是數(shù)據(jù)字節(jié)2等等。在非同步傳輸（批量或中斷）中，數(shù)據(jù)被發(fā)送到主機(jī)之前緩沖區(qū)必須被完全填滿(mǎn)并切換到下一個(gè)緩沖區(qū)。例外的情況是，當(dāng)前的緩沖區(qū)內(nèi)容將要被發(fā)送到主機(jī)時(shí)，由有效的EOT_N指示DMA傳輸?shù)慕Y(jié)束。清緩沖區(qū) 命令：F2h 處理：無(wú) 當(dāng)一個(gè)信息包完全接收之后，內(nèi)部端點(diǎn)緩沖區(qū)滿(mǎn)標(biāo)志置位，所有后續(xù)的包將被返回的NAK拒絕，當(dāng)微控制器已讀取數(shù)據(jù)，它應(yīng)當(dāng)通過(guò)清緩沖區(qū)命令來(lái)釋放緩沖區(qū)，當(dāng)緩沖區(qū)清空之后新的信息包就可被接受了。使緩沖區(qū)有效 命令：Fah 處理：無(wú) 當(dāng)微控制器已將數(shù)據(jù)寫(xiě)入IN緩沖區(qū)，它應(yīng)當(dāng)通過(guò)使緩沖區(qū)有效命令設(shè)置緩沖區(qū)滿(mǎn)標(biāo)志，這表示緩沖區(qū)內(nèi)的數(shù)據(jù)有效并可在接收到下一個(gè)IN標(biāo)志時(shí)將其送入主機(jī)。 設(shè)置端點(diǎn)狀態(tài) 命令：40-45h 處理：寫(xiě)1字節(jié) 當(dāng)一個(gè)停止控制的端點(diǎn)接收到SETUP標(biāo)志時(shí)自動(dòng)解除停止，而不管信息包的內(nèi)容如何，如果端點(diǎn)應(yīng)當(dāng)停在停止?fàn)顟B(tài)，微控制器可以重新停止它。當(dāng)一個(gè)停止的端點(diǎn)解除了停止，設(shè)置端點(diǎn)命令或接收到一個(gè)SETUP標(biāo)志，它同時(shí)被重新初始化將緩沖區(qū)刷新，如果是OUT緩沖區(qū)就等待一個(gè)DATA 0 PID，如果是IN緩沖區(qū)就寫(xiě)入一個(gè)DATA 0 PID，即使在解除停止時(shí)，將設(shè)置端點(diǎn)狀態(tài)寫(xiě)為0，也將初始化端點(diǎn)。停止 1 表示端點(diǎn)處于停止?fàn)顟B(tài) 2.3普通命令 發(fā)送恢復(fù) 命令：F6h 處理：無(wú) 發(fā)送一個(gè)上行數(shù)據(jù)流恢復(fù)信號(hào)10ms，該命令通常用于器件處于掛起狀態(tài)時(shí)，恢復(fù)命令后不跟讀出或?qū)懭氲臄?shù)據(jù) 讀當(dāng)前幀數(shù)目 該命令后跟1到2個(gè)讀出的字節(jié)并返回最后成功接收的SOF幀數(shù)目，幀數(shù)目為返回的低位字節(jié)。12